BD82QM67-SLJ4M Datasheet, PDF (844/934 Pages) Intel Corporation – Intel® 6 Series Chipset and Intel® 6 Series Chipset and

Serial Peripheral Interface (SPI)
21.4.14
SSFC—Software Sequencing Flash Control Register
(GbE LAN Memory Mapped Configuration Registers)
Memory Address: MBARB + 91h
Default Value:
000000h
Attribute:
Size:
R/W
24 bits
Bit
Description
23:19 Reserved
18:16
SPI Cycle Frequency (SCF) — R/W. This register sets frequency to use for all SPI
software sequencing cycles (write, erase, fast read, read status, etc.) except for the
read cycle which always run at 20 MHz.
000 = 20 MHz
001 = 33 MHz
All other values = Reserved.
This register is locked when the SPI Configuration Lock-Down bit is set.
15 Reserved
Data Cycle (DS) — R/W. When set to 1, there is data that corresponds to this
14 transaction. When 0, no data is delivered for this cycle, and the DBC and data fields
themselves are don’t cares.
13:8
Data Byte Count (DBC) — R/W. This field specifies the number of bytes to shift in or
out during the data portion of the SPI cycle. The valid settings (in decimal) are any
value from 0 to 3. The number of bytes transferred is the value of this field plus 1.
Note that when this field is 00b, then there is 1 byte to transfer and that 11b means
there are 4 bytes to transfer.
7 Reserved
Cycle Opcode Pointer (COP) — R/W. This field selects one of the programmed
6:4 opcodes in the Opcode Menu to be used as the SPI Command/Opcode. In the case of an
Atomic Cycle Sequence, this determines the second command.
Sequence Prefix Opcode Pointer (SPOP) — R/W. This field selects one of the two
programmed prefix opcodes for use when performing an Atomic Cycle Sequence. A
3 value of 0 points to the opcode in the least significant byte of the Prefix Opcodes
register. By making this programmable, the PCH supports flash devices that have
different opcodes for enabling writes to the data space versus status register.
Atomic Cycle Sequence (ACS) — R/W. When set to 1 along with the SCGO assertion,
the PCH will execute a sequence of commands on the SPI interface without allowing the
LAN component to arbitrate and interleave cycles. The sequence is composed of:
2
• Atomic Sequence Prefix Command (8-bit opcode only)
• Primary Command specified below by software (can include address and data)
• Polling the Flash Status Register (opcode 05h) until bit 0 becomes 0b.
The SPI Cycle in Progress bit remains set and the Cycle Done Status bit remains unset
until the Busy bit in the Flash Status Register returns 0.
SPI Cycle Go (SCGO) — R/WS. This bit always returns 0 on reads. However, a write to
this register with a ‘1’ in this bit starts the SPI cycle defined by the other bits of this
1
register. The “SPI Cycle in Progress” (SCIP) bit gets set by this action. Hardware must
ignore writes to this bit while the Cycle In Progress bit is set.
Hardware allows other bits in this register to be programmed for the same transaction
when writing this bit to 1. This saves an additional memory write.
0 Reserved
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