BD82QM67-SLJ4M Datasheet, PDF (352/934 Pages) Intel Corporation – Intel® 6 Series Chipset and Intel® 6 Series Chipset and

Electrical Characteristics
Figure 8-4. S3/M3 to S0 Timing Diagram
Source Dest
PCH
Board
PCH
Board
PCH
Board
PCH
Board
PCH
Board
Board
PCH
Board
PCH
Signal Name
SLP_S5#
SLP_S4#
SLP_S3#
SLP_A#
SLP_LAN#
VccASW
Vcc
CPU CPU VRM
CPU SVID
Board
CPU
VccCore_CPU
CPU VRM PCH
SYS_PWROK
Board
PCH
PWROK
Board
PCH
APWROK
PCH
CPU DRAMPWROK
Board
PCH
PCH
PCH
Board
CPU
25 MHz
Crystal Osc
PCH
Output Clocks
PROCPWRGD
PCH
CPU
Board
PCH
SUS_STAT#
THRMTRIP#
PCH CPU/Board
PLTRST#
Note: V_PROC_IO may go to Vboot at
this time, but can also stay at 0V
(default)
t205
t206
t208
t209
ignored
PCH
CPU
DMI
PROCPWRGD
Serial VID
Load
V_vid
stable
stable
t210
Assumes soft strap programmed to start at
CPUPWRGD - expected setting for SNB
honored
t211
TraininSgTRAP_SECTPU_FRleExSSEC^{KTPU_U_DRVOEDSNEMET_wDrOitNeEs_ACK}
Figure 8-5. S5/Moff - S5/M3 Timing Diagram
Source
PCH
PCH
PCH
PCH
PCH
Board
Board
Dest
Board
Board
Board
Board
Board
PCH
PCH
Signal Nam e
SLP_S5#
SLP_S4#
SLP_S3#
SLP_A#
SLP_LAN#
VccASW
APWROK
PCH
SPI Flash
SPI
PCH
Controller Link
CL_RST1#
(M obile O nly)
Could already be high before this sequence begins (to
sup p o rt W O L), b u t w ill n e ver g o h ig h la ter th a n S L P_A #
t207
t212
t213
352
Datasheet