BD82QM67-SLJ4M Datasheet, PDF (757/934 Pages) Intel Corporation – Intel® 6 Series Chipset and Intel® 6 Series Chipset and

PCI Express* Configuration Registers
19 PCI Express* Configuration
Registers
19.1
Note:
Note:
PCI Express* Configuration Registers
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
This section assumes the default PCI Express Function Number-to-Root Port mapping is
used. Function numbers for a given root port are assignable through the Root Port
Function Number and Hide for PCI Express Root Ports register (RCBA+0404h).
Register address locations that are not shown in Table 19-1, should be treated as
Reserved.
Table 19-1. PCI Express* Configuration Registers Address Map
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) (Sheet 1 of 3)
Offset Mnemonic
Register Name
00h–01h
02h–03h
04h–05h
06h–07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
18h–1Ah
1Bh
1Ch–1Dh
1Eh–1Fh
20h–23h
24h–27h
28h–2Bh
2Ch–2Fh
34h
VID
Vendor Identification
DID
Device Identification
PCICMD
PCISTS
PCI Command
PCI Status
RID
Revision Identification
PI
SCC
BCC
CLS
PLT
HEADTYP
BNUM
SLT
IOBL
SSTS
MBL
PMBL
PMBU32
PMLU32
CAPP
Programming Interface
Sub Class Code
Base Class Code
Cache Line Size
Primary Latency Timer
Header Type
Bus Number
Secondary Latency Timer
I/O Base and Limit
Secondary Status Register
Memory Base and Limit
Prefetchable Memory Base and Limit
Prefetchable Memory Base Upper 32
Bits
Prefetchable Memory Limit Upper 32
Bits
Capabilities List Pointer
3Ch–3Dh
INTR
Interrupt Information
Function 0–7
Default
8086h
See register
description
0000h
0010h
See register
description
00h
04h
06h
00h
00h
81h
000000h
00h
0000h
0000h
00000000h
00010001h
Attribute
RO
RO
R/W, RO
R/WC, RO
RO
RO
RO
RO
R/W
RO
RO
R/W
RO
R/W, RO
R/WC
R/W
R/W, RO
00000000h
R/W
00000000h
40h
See bit
description
R/W
RO
R/W, RO
Datasheet
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