BD82QM67-SLJ4M Datasheet, PDF (231/934 Pages) Intel Corporation – Intel® 6 Series Chipset and Intel® 6 Series Chipset and

Functional Description
Table 5-45. Enables for SMBus Slave Write and SMBus Host Events
Event
Slave Write to Wake/
SMI# Command
Slave Write to
SMLINK_SLAVE_SMI
Command
Any combination of Host
Status Register [4:1]
asserted
INTREN (Host
Control I/O Register,
Offset 02h, Bit 0)
SMB_SMI_EN (Host
Configuration Register,
D31:F3:Offset 40h,
Bit 1)
Event
Wake generated when asleep.
X
X
Slave SMI# generated when
awake (SMBUS_SMI_STS).
X
X
Slave SMI# generated when in
the S0 state (SMBUS_SMI_STS)
0
X
None
1
0
Interrupt generated
1
1
Host SMI# generated
Table 5-46. Enables for the Host Notify Command
HOST_NOTIFY_INTRE
N (Slave Control I/O
Register, Offset 11h,
Bit 0)
0
X
1
1
SMB_SMI_EN (Host
Config Register,
D31:F3:Off40h,
Bit 1)
X
X
0
1
HOST_NOTIFY_WKEN
(Slave Control I/O
Register, Offset 11h,
Bit 1)
0
1
X
X
Result
None
Wake generated
Interrupt generated
Slave SMI# generated
(SMBUS_SMI_STS)
5.20.5
SMBALERT#
SMBALERT# is multiplexed with GPIO[11]. When enable and the signal is asserted, the
PCH can generate an interrupt, an SMI#, or a wake event from S1–S5.
5.20.6
SMBus CRC Generation and Checking
If the AAC bit is set in the Auxiliary Control register, the PCH automatically calculates
and drives CRC at the end of the transmitted packet for write cycles, and will check the
CRC for read cycles. It will not transmit the contents of the PEC register for CRC. The
PEC bit must not be set in the Host Control register if this bit is set, or unspecified
behavior will result.
If the read cycle results in a CRC error, the DEV_ERR bit and the CRCE bit in the
Auxiliary Status register at Offset 0Ch will be set.
Datasheet
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