BD82QM67-SLJ4M Datasheet, PDF (16/934 Pages) Intel Corporation – Intel® 6 Series Chipset and Intel® 6 Series Chipset and

14.4
14.3.2 SDATA—Serial ATA Data Register (D31:F2)........................................... 585
14.3.2.1 PxSSTS—Serial ATA Status Register (D31:F2)........................ 585
14.3.2.2 PxSCTL—Serial ATA Control Register (D31:F2) ....................... 586
14.3.2.3 PxSERR—Serial ATA Error Register (D31:F2).......................... 587
AHCI Registers (D31:F2) .................................................................................. 588
14.4.1 AHCI Generic Host Control Registers (D31:F2) ...................................... 589
14.4.1.1 CAP—Host Capabilities Register (D31:F2) .............................. 590
14.4.1.2 GHC—Global PCH Control Register (D31:F2) .......................... 592
14.4.1.3 IS—Interrupt Status Register (D31:F2) ................................. 593
14.4.1.4 PI—Ports Implemented Register (D31:F2) ............................. 594
14.4.1.5 VS—AHCI Version Register (D31:F2) .................................... 595
14.4.1.6 EM_LOC—Enclosure Management Location Register (D31:F2) .. 595
14.4.1.7 EM_CTRL—Enclosure Management Control Register (D31:F2) .. 596
14.4.1.8 CAP2—HBA Capabilities Extended Register ............................ 597
14.4.1.9 VSP—Vendor Specific Register (D31:F2)................................ 597
14.4.1.10 RSTF—Intel^® RST Feature Capabilities Register...................... 598
14.4.2 Port Registers (D31:F2) ..................................................................... 599
14.4.2.1 PxCLB—Port [5:0] Command List Base Address Register
(D31:F2) .......................................................................... 602
14.4.2.2 PxCLBU—Port [5:0] Command List Base Address Upper
32-Bits Register (D31:F2) ................................................... 602
14.4.2.3 PxFB—Port [5:0] FIS Base Address Register (D31:F2) ............. 602
14.4.2.4 PxFBU—Port [5:0] FIS Base Address Upper 32-Bits
Register (D31:F2) .............................................................. 603
14.4.2.5 PxIS—Port [5:0] Interrupt Status Register (D31:F2) ............... 603
14.4.2.6 PxIE—Port [5:0] Interrupt Enable Register (D31:F2) ............... 605
14.4.2.7 PxCMD—Port [5:0] Command Register (D31:F2) .................... 606
14.4.2.8 PxTFD—Port [5:0] Task File Data Register (D31:F2) ............... 609
14.4.2.9 PxSIG—Port [5:0] Signature Register (D31:F2) ...................... 609
14.4.2.10 PxSSTS—Port [5:0] Serial ATA Status Register (D31:F2) ......... 610
14.4.2.11 PxSCTL — Port [5:0] Serial ATA Control Register (D31:F2) ...... 611
14.4.2.12 PxSERR—Port [5:0] Serial ATA Error Register (D31:F2) ........... 612
14.4.2.13 PxSACT—Port [5:0] Serial ATA Active Register (D31:F2) ......... 614
14.4.2.14 PxCI—Port [5:0] Command Issue Register (D31:F2) ............... 614
15 SATA Controller Registers (D31:F5) ....................................................................... 615
15.1 PCI Configuration Registers (SATA–D31:F5) ........................................................ 615
15.1.1 VID—Vendor Identification Register (SATA—D31:F5).............................. 616
15.1.2 DID—Device Identification Register (SATA—D31:F5) .............................. 616
15.1.3 PCICMD—PCI Command Register (SATA–D31:F5) .................................. 617
15.1.4 PCISTS — PCI Status Register (SATA–D31:F5) ...................................... 618
15.1.5 RID—Revision Identification Register (SATA—D31:F5) ............................ 618
15.1.6 PI—Programming Interface Register (SATA–D31:F5) .............................. 619
15.1.7 SCC—Sub Class Code Register (SATA–D31:F5)...................................... 619
15.1.8 BCC—Base Class Code Register
(SATA–D31:F5SATA–D31:F5) ............................................................. 619
15.1.9 PMLT—Primary Master Latency Timer Register
(SATA–D31:F5)................................................................................. 620
15.1.10 PCMD_BAR—Primary Command Block Base Address
Register (SATA–D31:F5) .................................................................... 620
15.1.11 PCNL_BAR—Primary Control Block Base Address Register
(SATA–D31:F5)................................................................................. 620
15.1.12 SCMD_BAR—Secondary Command Block Base Address
Register (SATA D31:F5) ..................................................................... 621
15.1.13 SCNL_BAR—Secondary Control Block Base Address
Register (SATA D31:F5) ..................................................................... 621
15.1.14 BAR—Legacy Bus Master Base Address Register
(SATA–D31:F5)................................................................................. 622
15.1.15 SIDPBA—SATA Index/Data Pair Base Address Register
(SATA–D31:F5)................................................................................. 622
15.1.16 SVID—Subsystem Vendor Identification Register
(SATA–D31:F5)................................................................................. 623
15.1.17 SID—Subsystem Identification Register (SATA–D31:F5) ......................... 623
15.1.18 CAP—Capabilities Pointer Register (SATA–D31:F5)................................. 623
15.1.19 INT_LN—Interrupt Line Register (SATA–D31:F5) ................................... 623
15.1.20 INT_PN—Interrupt Pin Register (SATA–D31:F5)..................................... 623
15.1.21 IDE_TIM—IDE Timing Register (SATA–D31:F5) ..................................... 624
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