BD82QM67-SLJ4M Datasheet, PDF (373/934 Pages) Intel Corporation – Intel® 6 Series Chipset and Intel® 6 Series Chipset and

Register and Memory Mapping
Table 9-4. Memory Decode Ranges from Processor Perspective (Sheet 3 of 3)
Memory Range
4 KB anywhere in 64-bit
address range
4 KB anywhere in 64-bit
address range
16 Bytes anywhere in 64-bit
address range
4 KB anywhere in 4 GB range
16 KB anywhere in 4 GB
range
Target
Thermal Reporting
Thermal Reporting
Intel^® MEI #1, #2
KT
Root Complex Register
Block (RCRB)
Dependency/Comments
Enable via standard PCI mechanism (Device 31:
Function 6 TBAR/TBARH)
Enable via standard PCI mechanism (Device 31:
Function 6 TBARB/TBARBH)
Enable via standard PCI mechanism (Device 22:
Function 1:0)
Enable via standard PCI mechanism (Device 22:
Function 3)
Enable via setting bit[0] of the Root Complex Base
Address register (D31:F0:offset F0h).
NOTES:
1.
Software must not attempt locks to memory mapped I/O ranges for USB EHCI or High
Precision Event Timers. If attempted, the lock is not honored, which means potential
deadlock conditions may occur.
2.
PCI is the target when the Boot BIOS Destination selection bits are set to 10b (Chipset
Config Registers:Offset 3401 bits 11:10). When PCI selected, the Firmware Hub Decode
Enable bits have no effect.
9.4.1
Boot-Block Update Scheme
The PCH supports a “top-block swap” mode that has the PCH swap the top block in the
FWH or SPI flash (the boot block) with another location. This allows for safe update of
the Boot Block (even if a power failure occurs). When the “Top Swap” Enable bit is set,
the PCH will invert A16 for cycles going to the upper two 64 KB blocks in the FWH or
appropriate address lines as selected in Boot Block Size (BOOT_BLOCK_SIZE) soft
strap for SPI.
Specifically for FHW, in this mode accesses to FFFF_0000h–FFFF_FFFFh are directed to
FFFE_0000h–FFFE_FFFFh and vice versa. When the Top Swap Enable bit is 0, the PCH
will not invert A16.
Specifically for SPI, in this mode the “Top-Block Swap” behavior is as described below.
When the Top Swap Enable bit is 0, the PCH will not invert any address bit.
Table 9-5. SPI Mode Address Swapping
BOOT_BLOCK_SIZE
Value
Accesses to
000 (64 KB)
FFFF_0000h–FFFF_FFFFh
001 (128 KB)
FFFE_0000h–FFFF_FFFFh
010 (256 KB)
FFFC_0000h–FFFF_FFFFh
011 (512 KB)
FFF8_0000h–FFFF_FFFFh
100 (1 MB)
101–111
FFF0_0000h–FFFF_FFFFh
Reserved
Being Directed to
FFFE_0000h–FFFE_FFFFh and vice
versa
FFFC_0000h–FFFD_FFFFh and vice
versa
FFF8_0000h–FFFB_FFFFh and vice
versa
FFF0_0000h–FFF7_FFFFh and vice
versa
FFE0_0000h–FFEF_FFFFh and vice
versa
Reserved
Datasheet
373