BD82QM67-SLJ4M Datasheet, PDF (172/934 Pages) Intel Corporation – Intel® 6 Series Chipset and Intel® 6 Series Chipset and

Functional Description
Table 5-25. Causes of SMI and SCI (Sheet 2 of 2)
Cause
TCO SMI – Message from processor
TCO SMI – NMI occurred (and NMIs
mapped to SMI)
TCO SMI – INTRUDER# signal goes
active
TCO SMI – Change of the BIOSWE
(D31:F0:DCh, Bit 0) bit from 0 to 1
TCO SMI – Write attempted to BIOS
BIOS_RLS written to
GBL_RLS written to
Write to B2h register
Periodic timer expires
64 ms timer expires
Enhanced USB Legacy Support Event
Enhanced USB Intel Specific Event
Serial IRQ SMI reported
Device monitors match address in its
range
SCI
No
No
No
No
No
Yes
No
No
No
No
No
No
No
No
SMBus Host Controller
No
SMBus Slave SMI message
No
SMBus SMBALERT# signal active
No
SMBus Host Notify message received No
(Mobile Only) BATLOW# assertion
Yes
Access microcontroller 62h/66h
No
SLP_EN bit written to 1
No
SPI Command Completed
No
Software Generated GPE
Yes
USB Per-Port Registers Write Enable
bit changes to 1
No
GPIO Lockdown Enable bit changes
from ‘1’ to ‘0’
No
SMI
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Additional Enables
none
NMI2SMI_EN=1
Where Reported
CPUSMI_STS
NMI2SMI_STS
INTRD_SEL=10
INTRD_DET
BLE=1
BIOSWR_STS
BIOSWE=1
GBL_EN=1
BIOS_EN=1
APMC_EN = 1
PERIODIC_EN=1
SWSMI_TMR_EN=1
LEGACY_USB2_EN = 1
INTEL_USB2_EN = 1
none
BIOSWR_STS
GBL_STS
BIOS_STS
APM_STS
PERIODIC_STS
SWSMI_TMR_STS
LEGACY_USB2_STS
INTEL_USB2_STS
SERIRQ_SMI_STS
none
DEVTRAP_STS
SMB_SMI_EN
Host Controller Enabled
none
none
HOST_NOTIFY_INTREN
BATLOW_EN=1
MCSMI_EN
SMI_ON_SLP_EN=1
None
SWGPE=1
USB2_EN=1,
Write_Enable_SMI_Enable=1
SMBus host status reg.
SMBUS_SMI_STS
SMBUS_SMI_STS
SMBUS_SMI_STS
HOST_NOTIFY_STS
BATLOW_STS
MCSMI_STS
SMI_ON_SLP_EN_STS
SPI_SMI_STS
SWGPE_STS
USB2_STS, Write Enable
Status
GPIO_UNLOCK_SMI_EN=1 GPIO_UNLOCK_SMI_STS
NOTES:
1.
SCI_EN must be 1 to enable SCI, except for BIOS_RLS. SCI_EN must be 0 to enable SMI.
2.
SCI can be routed to cause interrupt 9:11 or 20:23 (20:23 only available in APIC mode).
3.
GBL_SMI_EN must be 1 to enable SMI.
4.
EOS must be written to 1 to re-enable SMI for the next 1.
5.
The PCH must have SMI fully enabled when the PCH is also enabled to trap cycles. If SMI is not enabled in
conjunction with the trap enabling, then hardware behavior is undefined.
6.
Only GPI[15:0] may generate an SMI or SCI.
7.
When a power button override first occurs, the system will transition immediately to S5. The SCI will only
occur after the next wake to S0 if the residual status bit (PRBTNOR_STS) is not cleared prior to setting
SCI_EN.
8.
GBL_STS being set will cause an SCI, even if the SCI_EN bit is not set. Software must take great care not
to set the BIOS_RLS bit (which causes GBL_STS to be set) if the SCI handler is not in place.
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Datasheet