BD82QM67-SLJ4M Datasheet, PDF (18/934 Pages) Intel Corporation – Intel® 6 Series Chipset and Intel® 6 Series Chipset and

16.2
16.1.19 PWR_CAP—Power Management Capabilities Register
(USB EHCI—D29:F0, D26:F0) ............................................................. 648
16.1.20 PWR_CNTL_STS—Power Management Control/
Status Register (USB EHCI—D29:F0, D26:F0) ....................................... 649
16.1.21 DEBUG_CAPID—Debug Port Capability ID Register
(USB EHCI—D29:F0, D26:F0) ............................................................. 650
16.1.22 NXT_PTR2—Next Item Pointer #2 Register
(USB EHCI—D29:F0, D26:F0) ............................................................. 650
16.1.23 DEBUG_BASE—Debug Port Base Offset Register
(USB EHCI—D29:F0, D26:F0) ............................................................. 650
16.1.24 USB_RELNUM—USB Release Number Register
(USB EHCI—D29:F0, D26:F0) ............................................................. 650
16.1.25 FL_ADJ—Frame Length Adjustment Register
(USB EHCI—D29:F0, D26:F0) ............................................................. 651
16.1.26 PWAKE_CAP—Port Wake Capability Register
(USB EHCI—D29:F0, D26:F0) ............................................................. 652
16.1.27 LEG_EXT_CAP—USB EHCI Legacy Support Extended
Capability Register (USB EHCI—D29:F0, D26:F0) .................................. 653
16.1.28 LEG_EXT_CS—USB EHCI Legacy Support Extended
Control / Status Register (USB EHCI—D29:F0, D26:F0) .......................... 654
16.1.29 SPECIAL_SMI—Intel Specific USB 2.0 SMI Register
(USB EHCI—D29:F0, D26:F0) ............................................................. 656
16.1.30 ACCESS_CNTL—Access Control Register
(USB EHCI—D29:F0, D26:F0) ............................................................. 657
16.1.31 EHCIIR1—EHCI Initialization Register 1
(USB EHCI—D29:F0, D26:F0) ............................................................. 658
16.1.32 EHCIIR2—EHCI Initialization Register 2 (USB EHCI—D29:F0, D26:F0) ...... 658
16.1.33 FLR_CID—Function Level Reset Capability ID Register
(USB EHCI—D29:F0, D26:F0) ............................................................. 659
16.1.34 FLR_NEXT—Function Level Reset Next Capability
Pointer Register (USB EHCI—D29:F0, D26:F0) ...................................... 659
16.1.35 FLR_CLV—Function Level Reset Capability Length and
Version Register (USB EHCI—D29:F0, D26:F0)...................................... 660
16.1.36 FLR_CTRL—Function Level Reset Control Register
(USB EHCI—D29:F0, D26:F0) ............................................................. 660
16.1.37 FLR_STS—Function Level Reset Status Register
(USB EHCI—D29:F0, D26:F0) ............................................................. 661
16.1.38 EHCIIR3—EHCI Initialization Register 3 (USB EHCI—D29:F0, D26:F0) ...... 661
16.1.39 EHCIIR4—EHCI Initialization Register 4 (USB EHCI—D29:F0, D26:F0) ...... 661
Memory-Mapped I/O Registers .......................................................................... 662
16.2.1 Host Controller Capability Registers ..................................................... 662
16.2.1.1 CAPLENGTH—Capability Registers Length Register.................. 663
16.2.1.2 HCIVERSION—Host Controller Interface Version Number
Register............................................................................ 663
16.2.1.3 HCSPARAMS—Host Controller Structural Parameters Register... 663
16.2.1.4 HCCPARAMS—Host Controller Capability Parameters
Register............................................................................ 664
16.2.2 Host Controller Operational Registers ................................................... 665
16.2.2.1 USB2.0_CMD—USB 2.0 Command Register ........................... 666
16.2.2.2 USB2.0_STS—USB 2.0 Status Register.................................. 669
16.2.2.3 USB2.0_INTR—USB 2.0 Interrupt Enable Register .................. 671
16.2.2.4 FRINDEX—Frame Index Register .......................................... 672
16.2.2.5 CTRLDSSEGMENT—Control Data Structure Segment
Register............................................................................ 673
16.2.2.6 PERIODICLISTBASE—Periodic Frame List Base Address
Register............................................................................ 673
16.2.2.7 ASYNCLISTADDR—Current Asynchronous List Address
Register............................................................................ 674
16.2.2.8 CONFIGFLAG—Configure Flag Register .................................. 674
16.2.2.9 PORTSC—Port N Status and Control Register ......................... 675
16.2.3 USB 2.0-Based Debug Port Registers ................................................... 680
16.2.3.1 CNTL_STS—Control/Status Register...................................... 681
16.2.3.2 USBPID—USB PIDs Register ................................................ 683
16.2.3.3 DATABUF[7:0]—Data Buffer Bytes[7:0] Register .................... 683
16.2.3.4 CONFIG—Configuration Register........................................... 683
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