BD82QM67-SLJ4M Datasheet, PDF (551/934 Pages) Intel Corporation – Intel® 6 Series Chipset and Intel® 6 Series Chipset and

LPC Interface Bridge Registers (D31:F0)
13.10.16 GP_LVL3—GPIO Level for Input or Output 3 Register
Offset Address: GPIOBASE +48h
Default Value: 000000C0h
Lockable:
Yes
Attribute:
Size:
Power Well:
R/W
32-bit
Core for 0:7, 16:23,
Resume for 8:15, 24:31
Bit
Description
31:12
11:8
Always 0. No corresponding GPIO.
GP_LVL[75:72]— R/W.
These registers are implemented as dual read/write with dedicated storage each. Write
value will be stored in the write register, while read is coming from the read register
which will always reflect the value of the pin. If GPIO[n] is programmed to be an output
(using the corresponding bit in the GP_IO_SEL register), then the corresponding
GP_LVL[n] write register value will drive a high or low value on the output pin.
1 = high, 0 = low.
When configured in native mode (GPIO_USE_SEL[n] is 0), writes to these bits are
stored but have no effect to the pin value. The value reported in this register is
undefined when programmed as native mode.
7:4 Always 0. No corresponding GPIO.
GP_LVL[67:64] — R/W.
These registers are implemented as dual read/write with dedicated storage each. Write
value will be stored in the write register, while read is coming from the read register
which will always reflect the value of the pin. If GPIO[n] is programmed to be an output
(using the corresponding bit in the GP_IO_SEL register), then the corresponding
3:0 ^{GP_LVL[n] write register value will drive a high or low value on the output pin.}
1 = high, 0 = low.
When configured in native mode (GPIO_USE_SEL[n] is 0), writes to these bits are
stored but have no effect to the pin value. The value reported in this register is
undefined when programmed as native mode.
This register corresponds to GPIO[95:64]. Bit 0 corresponds to GPIO64.
13.10.17 GP_RST_SEL1—GPIO Reset Select Register
Offset Address: GPIOBASE +60h
Default Value: 01000000h
Lockable:
Yes
Attribute:
Size:
Power Well:
R/W
32-bit
Core for 0:7, 16:23,
Resume for 8:15, 24:31
Bit
Description
31:24
GP_RST_SEL[31:24] — R/W.
0 = Corresponding GPIO registers will be reset by PWROK deassertion, CF9h reset (06h
or 0Eh), or SYS_RESET# assertion.
1 = Corresponding GPIO registers will be reset by RSMRST# assertion only.
NOTE: GPIO[24] register bits are not cleared by CF9h reset by default.
23:16 Reserved
15:8
GP_RST_SEL[15:8] — R/W.
0 = Corresponding GPIO registers will be reset by PWROK deassertion, CF9h reset (06h
or 0Eh), or SYS_RESET# assertion.
1 = Corresponding GPIO registers will be reset by RSMRST# assertion only.
7:0 Reserved
Datasheet
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