BD82QM67-SLJ4M Datasheet, PDF (561/934 Pages) Intel Corporation – Intel® 6 Series Chipset and Intel® 6 Series Chipset and

SATA Controller Registers (D31:F2)
14.1.15
BAR—Legacy Bus Master Base Address Register
(SATA–D31:F2)
Address Offset: 20h–23h
Default Value: 00000001h
Attribute:
Size:
R/W, RO
32 bits
The Bus Master IDE interface function uses Base Address register 5 to request a 16-
byte I/O space to provide a software interface to the Bus Master functions. Only 12
bytes are actually used (6 bytes for primary, 6 bytes for secondary). Only bits [15:4]
are used to decode the address.
Bit
Description
31:16 Reserved
15:5
Base Address — R/W. This field provides the base address of the I/O space (16
consecutive I/O locations).
Base— R/W / RO. When SCC is 01h, this bit will be R/W resulting in requesting 16B of
4 I/O space. When SCC is not 01h, this bit will be Read Only 0, resulting in requesting
32B of I/O space.
3:1 Reserved
0
Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O
space.
14.1.16
ABAR/SIDPBA1—AHCI Base Address Register/Serial ATA
Index Data Pair Base Address (SATA–D31:F2)
When the programming interface is not IDE (that is, SCC is not 01h), this register is
named ABAR. When the programming interface is IDE, this register becomes SIDPBA.
Note that hardware does not clear those BA bits when switching from IDE component
to non-IDE component or vice versa. BIOS is responsible for clearing those bits to 0
since the number of writable bits changes after component switching (as indicated by a
change in SCC). In the case, this register will then have to be re-programmed to a
proper value.
14.1.16.1
When SCC is not 01h
When the programming interface is not IDE, the register represents a memory BAR
allocating space for the AHCI memory registers defined in Section 14.4.
.
Address Offset: 24–27h
Attribute:
R/W, RO
Default Value: 00000000h
Size:
32 bits
Bit
Description
31:11 Base Address (BA) — R/W. Base address of register memory space (aligned to 2 KB)
10:4 Reserved
3 Prefetchable (PF) — RO. Indicates that this range is not pre-fetchable
2:1
Type (TP) — RO. Indicates that this range can be mapped anywhere in 32-bit address
space.
0
Resource Type Indicator (RTE) — RO. Hardwired to 0 to indicate a request for
register memory space.
NOTE:
1.
The ABAR register must be set to a value of 0001_0000h or greater.
Datasheet
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