BD82QM67-SLJ4M Datasheet, PDF (862/934 Pages) Intel Corporation – Intel® 6 Series Chipset and Intel® 6 Series Chipset and

Thermal Sensor Registers (D31:F6)
22.2.10
PTA—PCH Temperature Adjust Register
Offset Address: TBARB+14h
Default Value: 0000h
Attribute:
Size:
R/W
16 bit
Bit
15:8
7:0
Description
PCH Slope — R/W. This field contains the PCH slope for calculating PCH temperature.
The bits are locked by AE.bit7 (offset 3Fh).
NOTE: When thermal reporting is enabled, BIOS must write DEh into this field.
Offset— R/W. This field contains the PCH offset for calculating PCH temperature. The
bits are locked by AE.bit7 (offset 3Fh).
NOTE: When thermal reporting is enabled, BIOS must write 87h into this field.
22.2.11
TRC—Thermal Reporting Control Register
Offset Address: TBARB+1Ah
Default Value: 0000h
Attribute:
Size:
R/W
16 bit
Bit
15:13
12
11:6
5
4
3
2
1
0
Description
Reserved
Thermal Data Reporting Enable — R/W.
0 = Disable
1 = Enable
Reserved
PCH Temperature Read Enable — R/W
0 = Disables reads of the PCH temperature.
1 = Enables reads of the PCH temperature.
Reserved
DIMM4 Temperature Read Enable — R/W
0 = Disables reads of DIMM4 temperature.
1 = Enables reads of DIMM4 temperature.
DIMM3 Temperature Read Enable — R/W
0 = Disables reads of DIMM3 temperature.
1 = Enables reads of DIMM3 temperature.
DIMM2 Temperature Read Enable — R/W
0 = Disables reads of DIMM2 temperature.
1 = Enables reads of DIMM2 temperature.
DIMM1 Temperature Read Enable — R/W
0 = Disables reads of DIMM1 temperature.
1 = Enables reads of DIMM1 temperature.
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