BD82QM67-SLJ4M Datasheet, PDF (717/934 Pages) Intel Corporation – Intel® 6 Series Chipset and Intel® 6 Series Chipset and

Integrated Intel^® High Definition Audio Controller Registers
17.1.2.13
INTSTS—Interrupt Status Register
(Intel^® High Definition Audio Controller—D27:F0)
Memory Address:HDBAR + 24h
Default Value: 00000000h
Attribute:
Size:
RO
32 bits
Bit
31
30
29:8
Description
Global Interrupt Status (GIS) — RO. This bit is an OR of all the interrupt status bits
in this register.
NOTE: This bit is not affected by the D3_HOT to D0 transition.
Controller Interrupt Status (CIS) — RO. Status of general controller interrupt.
1 = Interrupt condition occurred due to a Response Interrupt, a Response Buffer
Overrun Interrupt, or a SDIN State Change event. The exact cause can be
determined by interrogating other registers. This bit is an OR of all of the stated
interrupt status bits for this register.
NOTES:
1.
This bit is set regardless of the state of the corresponding interrupt enable bit,
but a hardware interrupt will not be generated unless the corresponding enable
bit is set.
2.
This bit is not affected by the D3_HOT to D0 transition.
Reserved
Stream Interrupt Status (SIS) — RO.
1 = Interrupt condition occurred on the corresponding stream. This bit is an OR of all of
the stream’s interrupt status bits.
NOTE: These bits are set regardless of the state of the corresponding interrupt enable
bits.
The streams are numbered and the SIE bits assigned sequentially, based on their order
7:0 ^{in the register set.}
Bit 0 = input stream 1
Bit 1 = input stream 2
Bit 2 = input stream 3
Bit 3 = input stream 4
Bit 4 = output stream 1
Bit 5 = output stream 2
Bit 6 = output stream 3
Bit 7 = output stream 4
17.1.2.14
WALCLK—Wall Clock Counter Register
(Intel^® High Definition Audio Controller—D27:F0)
Memory Address:HDBAR + 30h
Default Value: 00000000h
Attribute:
Size:
RO
32 bits
Bit
31:0
Description
Wall Clock Counter — RO. A 32-bit counter that is incremented on each link Bit Clock
period and rolls over from FFFF FFFFh to 0000 0000h. This counter will roll over to 0
with a period of approximately 179 seconds.
This counter is enabled while the Bit Clock bit is set to 1. Software uses this counter to
synchronize between multiple controllers. Will be reset on controller reset.
Datasheet
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