BD82QM67-SLJ4M Datasheet, PDF (568/934 Pages) Intel Corporation – Intel® 6 Series Chipset and Intel® 6 Series Chipset and

SATA Controller Registers (D31:F2)
14.1.28 MSIMA— Message Signaled Interrupt Message
Address Register (SATA–D31:F2)
Address Offset: 84h–87h
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
Note:
There is no support for MSI when the software is operating in legacy (IDE) mode when
AHCI is not enabled. Prior to switching from AHCI to IDE mode, software must make
sure that MSI is disabled.
Bits
31:2
1:0
Description
Address (ADDR) — R/W. Lower 32 bits of the system specified message address,
always DWORD aligned.
Reserved
14.1.29 MSIMD—Message Signaled Interrupt Message
Data Register (SATA–D31:F2)
Address Offset: 88h–89h
Default Value: 0000h
Attribute:
Size:
R/W
16 bits
Note:
There is no support for MSI when the software is operating in legacy (IDE) mode when
AHCI is not enabled. Prior to switching from AHCI to IDE mode, software must make
sure that MSI is disabled.
Bits
15:0
Description
Data (DATA) — R/W. This 16-bit field is programmed by system software if MSI is
enabled. Its content is driven onto the lower word of the data bus of the MSI memory
write transaction. Note that when the MME field is set to ‘001’ or ‘010’, bit [0] and bits
[1:0] respectively of the MSI memory write transaction will be driven based on the
source of the interrupt rather than from MD[2:0]. See the description of the MME field.
568
Datasheet