BD82QM67-SLJ4M Datasheet, PDF (534/934 Pages) Intel Corporation – Intel® 6 Series Chipset and Intel® 6 Series Chipset and

LPC Interface Bridge Registers (D31:F0)
13.8.3.10
ALT_GP_SMI_STS—Alternate GPI SMI Status Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE +3Ah
0000h
No
Resume
Attribute:
Size:
Usage:
R/WC
16-bit
ACPI or Legacy
Bit
15:0
Description
Alternate GPI SMI Status — R/WC. These bits report the status of the corresponding
GPIOs.
0 = Inactive. Software clears this bit by writing a 1 to it.
1 = Active
These bits are sticky. If the following conditions are true, then an SMI# will be
generated and the GPE0_STS bit set:
• The corresponding bit in the ALT_GPI_SMI_EN register (PMBASE + 38h) is set
• The corresponding GPIO must be routed in the GPI_ROUT register to cause an SMI.
• The corresponding GPIO must be implemented.
All bits are in the resume well. Default for these bits is dependent on the state of the
GPIO pins.
13.8.3.11
GPE_CNTL—General Purpose Control Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE +42h
00h
No
Bits 0–1, 3–7: Resume
Bit 2: RTC
Attribute:
Size:
Usage:
R/W
8-bit
ACPI or Legacy
Bit
Description
7:2 Reserved
GPIO27_POL — R/W. This bit controls the polarity of the GPIO27 pin needed to set the
GPIO27_STS bit.
2 0 = GPIO27 = 0 will set the GPIO27_STS bit.
1 = GPIO27 = 1 will set the GPIO27_STS bit
This bit is cleared by RTCRST# assertion.
SWGPE_CTRL— R/W. This bit allows software to control the assertion of SWGPE_STS
bit. This bit is used by hardware as the level input signal for the SWGPE_STS bit in the
GPE0_STS register. When SWGPE_CTRL is 1, SWGPE_STS will be set to 1, and writes to
SWGPE_STS with a value of 1 to clear SWGPE_STS will result in SWGPE_STS being set
1
back to 1 by hardware. When SWGPE_CTRL is 0, writes to SWGPE_STS with a value of
1 will clear SWGPE_STS to 0.
In addition to being cleared by RSMRST# assertion, the PCH also clears this bit due to a
Power Button Override event, Intel ME Initiated Power Button Override, Intel ME
Initiated Host Reset with Power down, SMBus unconditional power down, processor
thermal trip event, or due to an internal thermal sensor catastrophic condition.
0 Reserved
534
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