BD82QM67-SLJ4M Datasheet, PDF (452/934 Pages) Intel Corporation – Intel® 6 Series Chipset and Intel® 6 Series Chipset and

LPC Interface Bridge Registers (D31:F0)
Bit
11
10:9
8
7
6
5
4
3
2:0
Description
Signaled Target Abort (STA) — R/WC.
0 = Target abort Not generated on the backbone.
1 = LPC bridge generated a completion packet with target abort status on the
backbone.
DEVSEL# Timing Status (DEV_STS) — RO.
01 = Medium Timing.
Data Parity Error Detected (DPED) — R/WC.
0 = All conditions listed below Not met.
1 = Set when all three of the following conditions are met:
• LPC bridge receives a completion packet from the backbone from a previous
request,
• Parity error has been detected (D31:F0:06, bit 15)
• PCICMD.PERE bit (D31:F0:04, bit 6) is set.
Fast Back to Back Capable (FBC) — RO. Hardwired to 0.
Reserved
66 MHz Capable (66MHZ_CAP) — RO. Hardwired to 0.
Capabilities List (CLIST) — RO. Capability list exists on the LPC bridge.
Interrupt Status (IS) — RO. The LPC bridge does not generate interrupts.
Reserved
13.1.5
RID—Revision Identification Register (LPC I/F—D31:F0)
Offset Address: 08h
Default Value: See bit description
Attribute:
Size:
R/WO
8 bits
Bit
Description
7:0
Revision ID (RID) — R/WO. See the Intel^® 6 Series Chipset and Intel^® C200 Series
Chipset Specification Update for the value of the RID Register.
13.1.6
PI—Programming Interface Register (LPC I/F—D31:F0)
Offset Address: 09h
Default Value: 00h
Attribute:
Size:
RO
8 bits
Bit
Description
7:0 Programming Interface — RO.
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