BD82QM67-SLJ4M Datasheet, PDF (377/934 Pages) Intel Corporation – Intel® 6 Series Chipset and Intel® 6 Series Chipset and

Chipset Configuration Registers
10.1.1
CIR0—Chipset Initialization Register 0
Offset Address: 0050–0053h
Default Value: 00000000h
Attribute:
Size:
R/WL
32-bit
10.1.2
Bit
31
30:0
Description
TC Lock-Down (TCLOCKDN)— R/WL. When set to 1, certain DMI configuration
registers are locked down by this and cannot be written. Once set to 1, this bit can
only be cleared by a PLTRST#.
CIR0 Field 0— R/WL. BIOS must set this field. Bits locked by TCLOCKDN.
RPC—Root Port Configuration Register
Offset Address: 0400–0403h
Attribute:
Default Value: 0000000yh (y = 00xxb) Size:
R/W, RO
32-bit
Bit
31:12
11
10:8
7:4
3:2
Description
Reserved
GbE Over PCIe Root Port Enable (GBEPCIERPEN) — R/W.
0 = GbE MAC/PHY communication is not enabled over PCI Express.
1 = The PCI Express port selected by the GBEPCIEPORTSEL register will be used for
GbE MAC/PHY over PCI Express communication
The default value for this register is set by the GBE_PCIE_EN soft strap.
Note: GbE and PCIe will use the output of this register and not the soft strap
GbE Over PCIe Root Port Select (GBEPCIERPSEL) — R/W. If the GBEPCIERPEN
is a ‘1’, then this register determines which port is used for GbE MAC/PHY
communication over PCI Express. This register is set by soft strap and is writable to
support separate PHY on motherboard and docking station.
111 = Port 8 (Lane 7)
110 = Port 7 (Lane 6)
101 = Port 6 (Lane 5)
100 = Port 5 (Lane 4)
101 = Port 4 (Lane 3)
010 = Port 3 (Lane 2)
001 = Port 2 (Lane 1)
000 = Port 1 (Lane 0)
The default value for this register is set by the GBE_PCIEPORTSEL[2:0] soft strap.
Note: GbE and PCIe will use the output of this register and not the soft strap
Reserved
Port Configuration2 (PC2) — RO. This controls how the PCI bridges are organized
in various modes of operation for Ports 5–8. For the following mappings, if a port is
not shown, it is considered a x1 port with no connection.
This bit is set by the PCIEPCS2[1:0] soft strap.
11 = 1 x4, Port 5 (x4)
10 = 2 x2, Port 5 (x2), Port 7 (x2)
01 = 1x2 and 2x1s, Port 5 (x2), Port 7 (x1) and Port 8(x1)
00 = 4 x1s, Port 5 (x1), Port 6 (x1), Port 7 (x1) and Port 8 (x1)
Datasheet
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