BD82QM67-SLJ4M Datasheet, PDF (178/934 Pages) Intel Corporation – Intel® 6 Series Chipset and Intel® 6 Series Chipset and

Functional Description
5.13.7.5
Sx-G3-Sx, Handling Power Failures
Depending on when the power failure occurs and how the system is designed, different
transitions could occur due to a power failure.
The AFTERG3_EN bit provides the ability to program whether or not the system should
boot once power returns after a power loss event. If the policy is to not boot, the
system remains in an S5 state (unless previously in S4). There are only three possible
events that will wake the system after a power failure.
1. PWRBTN#: PWRBTN# is always enabled as a wake event. When RSMRST# is low
(G3 state), the PWRBTN_STS bit is reset. When the PCH exits G3 after power
returns (RSMRST# goes high), the PWRBTN# signal
standby goes high before RSMRST# goes high) and
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2. RI#: RI# does not have an internal pull-up. Therefore, if this signal is enabled as a
wake event, it is important to keep this signal powered during the power loss
event. If this signal goes low (active), when power returns the RI_STS bit is set and
the system interprets that as a wake event.
3. RTC Alarm: The RTC_EN bit is in the RTC well and is preserved after a power loss.
Like PWRBTN_STS the RTC_STS bit is cleared when RSMRST# goes low.
The PCH monitors both PCH PWROK and RSMRST# to detect for power failures. If PCH
PWROK goes low, the PWROK_FLR bit is set. If RSMRST# goes low, PWR_FLR is set.
Note:
Although PME_EN is in the RTC well, this signal cannot wake the system after a power
loss. PME_EN is cleared by RTCRST#, and PME_STS is cleared by RSMRST#.
Table 5-29. Transitions Due to Power Failure
State at Power Failure
S0, S1, S3
S4
S5
Deep S4/S5
AFTERG3_EN bit
1
0
1
0
1
0
1
0
Transition When Power Returns
S5
S0
S4
S0
S5
S0
Deep S4/S5¹
S0
NOTE:
1.
Entry state to Deep S4/S5 is preserved through G3 allowing resume from Deep S4/S5 to
take appropriate path (that is, return to S4 or S5).
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