BD82QM67-SLJ4M Datasheet, PDF (872/934 Pages) Intel Corporation – Intel® 6 Series Chipset and Intel® 6 Series Chipset and

Intel® Management Engine Subsystem Registers (D22:F[3:0])
23.1.1.5
RID—Revision Identification Register
(Intel^® MEI 1—D22:F0)
Offset Address: 08h
Default Value: See bit description
Attribute:
Size:
RO
8 bits
23.1.1.6
Bit
Description
7:0
Revision ID — RO. See the Intel^® 6 Series Chipset and Intel^® C200 Series Chipset
Specification Update for the value of the RID Register.
CC—Class Code Register
(Intel^® MEI 1—D22:F0)
Address Offset: 09h–0Bh
Default Value: 078000h
Attribute:
Size:
RO
24 bits
23.1.1.7
Bit
23:16
15:8
7:0
Description
Base Class Code (BCC) — RO. Indicates the base class code of the Intel MEI device.
Sub Class Code (SCC) — RO. Indicates the sub class code of the Intel MEI device.
Programming Interface (PI) — RO. Indicates the programming interface of the Intel
MEI device.
HTYPE—Header Type Register
(Intel^® MEI 1—D22:F0)
Address Offset: 0Eh
Default Value: 80h
Attribute:
Size:
RO
8 bits
23.1.1.8
Bit
Description
7
Multi-Function Device (MFD) — RO. Indicates the Intel MEI host controller is part of
a multifunction device.
6:0 Header Layout (HL) — RO. Indicates that the Intel MEI uses a target device layout.
MEI0_MBAR—MEI0 MMIO Base Address Register
(Intel^® MEI 1—D22:F0)
Address Offset: 10h–17h
Default Value: 0000000000000004h
Attribute:
Size:
R/W, RO
64 bits
This register allocates space for the MEI0 memory mapped registers.
Bit
63:4
3
2:1
0
Description
Base Address (BA) — R/W. Software programs this field with the base address of
this region.
Prefetchable Memory (PM) — RO. Indicates that this range is not pre-fetchable.
Type (TP) — RO. Set to 10b to indicate that this range can be mapped anywhere in
64-bit address space.
Resource Type Indicator (RTE) — RO. Indicates a request for register memory
space.
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