BD82QM67-SLJ4M Datasheet, PDF (831/934 Pages) Intel Corporation – Intel® 6 Series Chipset and Intel® 6 Series Chipset and

Serial Peripheral Interface (SPI)
Bit
Description
7:5 Reserved
Write Enable on Write Status (LWEWS) — R/W. This register is locked by the Vendor
Component Lock (LVCL) bit.
0 = No automatic write of 00h will be made to the SPI flash’s status register)
1 = A write of 00h to the SPI flash’s status register will be sent on EVERY write and
erase to the SPI flash. 06h 01h 00h is the opcode sequence used to unlock the
Status register.
4
NOTES:
1.
This bit should not be set to 1 if there are non-volatile bits in the SPI flash’s
status register. This may lead to premature flash wear out.
2.
This is not an atomic sequence. If the SPI component’s status register is non-
volatile, then BIOS should issue an atomic software sequence cycle to unlock the
flash part.
3.
Bit 3 and bit 4 should NOT be both set to 1.
Lower Write Status Required (LWSR) — R/W. This register is locked by the Vendor
Component Lock (LVCL) bit.
0 = No automatic write of 00h will be made to the SPI flash’s status register)
1 = A write of 00h to the SPI flash’s status register will be sent on EVERY write and
erase to the SPI flash. 50h 01h 00h is the opcode sequence used to unlock the
Status register.
3
NOTES:
1.
This bit should not be set to 1 if there are non volatile bits in the SPI flash’s
status register. This may lead to premature flash wear out.
2.
This is not an atomic sequence. If the SPI component’s status register is non-
volatile, then BIOS should issue an atomic software sequence cycle to unlock the
flash part.
3.
Bit 3 and bit 4 should NOT be both set to 1.
Lower Write Granularity (LWG) — R/W. This register is locked by the Vendor
Component Lock (LVCL) bit.
0 = 1 Byte
1 = 64 Byte
2 NOTES:
1.
If more than one Flash component exists, this field must be set to the lowest
common write granularity of the different Flash components.
2.
If using 64 B write, BIOS must ensure that multiple byte writes do not occur over
256 B boundaries. This will lead to corruption as the write will wrap around the
page boundary on the SPI flash part. This is a a feature page writable SPI flash.
Lower Block/Sector Erase Size (LBES)— R/W. This field identifies the erasable
sector size for all Flash components.
00 = 256 Byte
01 = 4 KB
1:0
10 = 8 KB
11 = 64 KB
This register is locked by the Vendor Component Lock (LVCL) bit.
Hardware takes no action based on the value of this register. The contents of this
register are to be used only by software and can be read in the HSFSTS.BERASE register
in both the BIOS and the GbE program registers if FLA is less than FPBA.
Datasheet
831