BD82QM67-SLJ4M Datasheet, PDF (787/934 Pages) Intel Corporation – Intel® 6 Series Chipset and Intel® 6 Series Chipset and

PCI Express* Configuration Registers
19.1.48
PMCS—PCI Power Management Control and Status
Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: A4h–A7h
Default Value: 00000000h
Attribute:
Size:
R/W, RO
32 bits
Bit
Description
31:24 Reserved
23
Bus Power / Clock Control Enable (BPCE) — Reserved per PCI Express* Base
Specification, Revision 1.0a.
22 B2/B3 Support (B23S) — Reserved per PCI Express* Base Specification, Revision 1.0a.
21:16 Reserved
PME Status (PMES) — RO.
15
1 = Indicates a PME was received on the downstream link.
14:9 Reserved
PME Enable (PMEE) — R/W.
1 = Indicates PME is enabled. The root port takes no action on this bit, but it must be
8
R/W for some legacy operating systems to enable PME# on devices connected to
this root port.
This bit is sticky and resides in the resume well. The reset for this bit is RSMRST# which
is not asserted during a warm reset.
7:2 Reserved
Power State (PS) — R/W. This field is used both to determine the current power state
of the root port and to set a new power state. The values are:
00 = D0 state
11 = D3_HOT state
1:0
NOTE: When in the D3_HOT state, the controller’s configuration space is available, but
the I/O and memory spaces are not. Type 1 configuration cycles are also not
accepted. Interrupts are not required to be blocked as software will disable
interrupts prior to placing the port into D3_HOT. If software attempts to write a
‘10’ or ‘01’ to these bits, the write will be ignored.
Datasheet
787