BD82QM67-SLJ4M Datasheet, PDF (741/934 Pages) Intel Corporation – Intel® 6 Series Chipset and Intel® 6 Series Chipset and

SMBus Controller Registers (D31:F3)
18.1.4
Note:
PCISTS—PCI Status Register (SMBus—D31:F3)
Address:
06h–07h
Default Value: 0280h
Attributes:
Size:
RO
16 bits
For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to
the bit has no effect.
Bit
15
14
13
12
11
10:9
8
7
6
5
4
3
2:0
Description
Detected Parity Error (DPE) — R/WC.
0 = No parity error detected.
1 = Parity error detected.
Signaled System Error (SSE) — R/WC.
0 = No system error detected.
1 = System error detected.
Received Master Abort (RMA) — RO. Hardwired to 0.
Received Target Abort (RTA) — RO. Hardwired to 0.
Signaled Target Abort (STA) — RO. Hardwired to 0.
DEVSEL# Timing Status (DEVT) — RO. This 2-bit field defines the timing for
DEVSEL# assertion for positive decode.
01 = Medium timing.
Data Parity Error Detected (DPED) — RO. Hardwired to 0.
Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1.
User Definable Features (UDF) — RO. Hardwired to 0.
66 MHz Capable (66MHZ_CAP) — RO. Hardwired to 0.
Capabilities List (CAP_LIST) — RO. Hardwired to 0 because there are no capability list
structures in this function
Interrupt Status (INTS) — RO. This bit indicates that an interrupt is pending. It is
independent from the state of the Interrupt Enable bit in the PCI Command register.
Reserved
18.1.5
RID—Revision Identification Register (SMBus—D31:F3)
Offset Address: 08h
Default Value: See bit description
Attribute:
Size:
RO
8 bits
Bit
Description
7:0
Revision ID — RO. See the Intel^® 6 Series Chipset and Intel^® C200 Series Chipset
Specification Update for the value of the RID Register.
Datasheet
741