BD82QM67-SLJ4M Datasheet, PDF (652/934 Pages) Intel Corporation – Intel® 6 Series Chipset and Intel® 6 Series Chipset and

EHCI Controller Registers (D29:F0, D26:F0)
16.1.26
PWAKE_CAP—Port Wake Capability Register
(USB EHCI—D29:F0, D26:F0)
Address Offset:
Default Value:
Default Value:
Function Level Reset:
62–63h
01FFh
07FFh
No
Attribute:
Size:
R/W
16 bits
This register is in the suspend power well. The intended use of this register is to
establish a policy about which ports are to be used for wake events. Bit positions 1–
8(D29) or 1–6(D26) in the mask correspond to a physical port implemented on the
current EHCI controller. A 1 in a bit position indicates that a device connected below the
port can be enabled as a wake-up device and the port may be enabled for disconnect/
connect or overcurrent events as wake-up events. This is an information-only mask
register. The bits in this register do not affect the actual operation of the EHCI host
controller. The system-specific policy can be established by BIOS initializing this
register to a system-specific value. System software uses the information in this
register when enabling devices and ports for remote wake-up.
These bits are not reset by a D3-to-D0 warm rest or a core well reset.
Bit D
escription
15:9 (D29)
15:7 (D26)
Reserved.
8:1 (D29)
6:1 (D26)
Port Wake Up Capability Mask — R/W. Bit positions 1 through 8 (Device 29) or
1 through 6(Device 26) correspond to a physical port implemented on this host
controller. For example, bit position 1 corresponds to port 1, bit position 2
corresponds to port 2, etc.
0
Port Wake Implemented — R/W. A 1 in this bit indicates that this register is
implemented to software.
652
Datasheet