BD82QM67-SLJ4M Datasheet, PDF (49/934 Pages) Intel Corporation – Intel® 6 Series Chipset and Intel® 6 Series Chipset and

Introduction
Manageability
In addition to Intel AMT the PCH integrates several functions designed to manage the
system and lower the total cost of ownership (TCO) of the system. These system
management functions are designed to report errors, diagnose the system, and recover
from system lockups without the aid of an external microcontroller.
• TCO Timer. The PCH’s integrated programmable TCO timer is used to detect
system locks. The first expiration of the timer generates an SMI# that the system
can use to recover from a software lock. The second expiration of the timer causes
a system reset to recover from a hardware lock.
• Processor Present Indicator. The PCH looks for the processor to fetch the first
instruction after reset. If the processor does not fetch the first instruction, the PCH
will reboot the system.
• ECC Error Reporting. When detecting an ECC error, the host controller has the
ability to send one of several messages to the PCH. The host controller can instruct
the PCH to generate either an SMI#, NMI, SERR#, or TCO interrupt.
• Function Disable. The PCH provides the ability to disable the following integrated
functions: LAN, USB, LPC, Intel HD Audio, SATA, PCI Express or SMBus. Once
disabled, these functions no longer decode I/O, memory, or PCI configuration
space. Also, no interrupts or power management events are generated from the
disabled functions.
• Intruder Detect. The PCH provides an input signal (INTRUDER#) that can be
attached to a switch that is activated by the system case being opened. The PCH
can be programmed to generate an SMI# or TCO interrupt due to an active
INTRUDER# signal.
System Management Bus (SMBus 2.0)
The PCH contains an SMBus Host interface that allows the processor to communicate
with SMBus slaves. This interface is compatible with most I²C devices. Special I²C
commands are implemented.
The PCH’s SMBus host controller provides a mechanism for the processor to initiate
communications with SMBus peripherals (slaves). Also, the PCH supports slave
functionality, including the Host Notify protocol. Hence, the host controller supports
eight command protocols of the SMBus interface (see System Management Bus
(SMBus) Specification, Version 2.0): Quick Command, Send Byte, Receive Byte, Write
Byte/Word, Read Byte/Word, Process Call, Block Read/Write, and Host Notify.
The PCH’s SMBus also implements hardware-based Packet Error Checking for data
robustness and the Address Resolution Protocol (ARP) to dynamically provide address
to all SMBus devices.
Intel^® High Definition Audio Controller
The Intel^® High Definition Audio Specification defines a digital interface that can be
used to attach different types of codecs, such as audio and modem codecs. The PCH
Intel^® HD Audio controller supports up to 4 codecs. The link can operate at either 3.3 V
or 1.5 V.
With the support of multi-channel audio stream, 32-bit sample depth, and sample rate
up to 192 kHz, the Intel HD Audio controller provides audio quality that can deliver CE
levels of audio experience. On the input side, the PCH adds support for an array of
microphones.
Datasheet
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