BD82QM67-SLJ4M Datasheet, PDF (402/934 Pages) Intel Corporation – Intel® 6 Series Chipset and Intel® 6 Series Chipset and

Chipset Configuration Registers
10.1.38
DEEP_S4_POL—Deep S4/S5 From S4 Power Policies
Register
Offset Address: 332C–332Fh
Default Value: 00000000h
Attribute:
Size:
R/W
32-bit
This register is in the RTC power well and is reset by RTCRST# assertion.
Bit
31:2
1
0
Description
Reserved
Deep S4/S5 From S4 Enable in DC Mode (DPS4_EN_DC) — R/W. A '1' in this bit
enables the platform to enter Deep S4/S5 while operating in S4 on DC power (based
on the AC_PRESENT pin value).
Deep S4/S5 From S4 Enable in AC Mode (DPS4_EN_AC) — R/W. A '1' in this bit
enables the platform to enter Deep S4/S5 while operating in S4 on AC power (based
on the AC_PRESENT pin value). Required to be programmed to 0 on mobile.
10.1.39
DEEP_S5_POL—Deep S4/S5 From S5 Power Policies
Register
Offset Address: 3330–3333h
Default Value: 00000000h
Attribute:
Size:
R/W
32-bit
This register is in the RTC power well and is reset by RTCRST# assertion.
Bit
31:16
15
14
13:0
Description
Reserved
Deep S4/S5 From S5 Enable in DC Mode (DPS5_EN_DC) — R/W. A '1' in this bit
enables the platform to enter Deep S4/S5 while operating in S5 on DC power (based
on the AC_PRESENT pin value).
Deep S4/S5 From S5 Enable in AC Mode (DPS5_EN_AC) — R/W. A '1' in this bit
enables the platform to enter Deep S4/S5 while operating in S5 on AC power (based
on the AC_PRESENT pin value). Required to be programmed to 0 on mobile.
Reserved
402
Datasheet