BD82QM67-SLJ4M Datasheet, PDF (645/934 Pages) Intel Corporation – Intel® 6 Series Chipset and Intel® 6 Series Chipset and

EHCI Controller Registers (D29:F0, D26:F0)
16.1.9
PMLT—Primary Master Latency Timer Register
(USB EHCI—D29:F0, D26:F0)
Address Offset: 0Dh
Default Value: 00h
Attribute:
Size:
RO
8 bits
Bit D
escription
Master Latency Timer Count (MLTC) — RO. Hardwired to 00h. Because the EHCI
7:0 controller is internally implemented with arbitration on an interface (and not PCI), it
does not need a master latency timer.
16.1.10
HEADTYP—Header Type Register
(USB EHCI—D29:F0, D26:F0)
Address Offset: 0Eh
Default Value: 80h
Attribute:
Size:
RO
8 bits
Bit
Description
Multi-Function Device — RO. When set to ‘1’ indicates this is a multifunction device:
7
0 = Single-function device
1 = Multi-function device.
6:0
Configuration Layout. Hardwired to 00h, which indicates the standard PCI configuration
layout.
16.1.11
MEM_BASE—Memory Base Address Register
(USB EHCI—D29:F0, D26:F0)
Address Offset: 10h–13h
Default Value: 00000000h
Attribute:
Size:
R/W, RO
32 bits
Bit D
escription
31:10
Base Address — R/W. Bits [31:10] correspond to memory address signals [31:10],
respectively. This gives 1-KB of locatable memory space aligned to 1-KB boundaries.
9:4 Reserved
3
Prefetchable — RO. Hardwired to 0 indicating that this range should not be
prefetched.
2:1
Type — RO. Hardwired to 00b indicating that this range can be mapped anywhere
within 32-bit address space.
0
Resource Type Indicator (RTE) — RO. Hardwired to 0 indicating that the base
address field in this register maps to memory space.
Datasheet
645