I347-AT4 Datasheet, PDF (93/148 Pages) Intel Corporation – Intel® Ethernet Network Connection I347-AT4 Datasheet

Programmer’s Visible State—I347-AT4
4.1.28 MAC Specific Control Register 1 - Page 2, Register 16
Bits
Field
15:14
Copper Transmit
FIFO Depth
13
Reserved
12
RCLK Frequency
Select
11
RCLK Link Down
Disable
10
Reserved
9
RCLK2 Select
8
RCLK1 Select
Copper
7
Reference Clock
Source Select
6
Reserved
5:4
Reserved
MAC
3
Interface Power
Down
2:0
Reserved
Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
HW Rst SW Rst
Description
00 = ± 16 Bits
0x1
Retain
01 = ± 24 Bits
10 = ± 32 Bits
11 = ± 40 Bits
0x0
Update Set to 0
0x0
Retain
0 = 25 MHz
1 = 125 MHz
0 = RCLK outputs 25 MHz clock during link down and
0x0
Retain
10BASE-T.
1 = RCLK low during link down and 10BASE-T.
0x0
Retain
Set to 0
The highest numbered port with this bit set will output the
clock.
0x0
Retain
The 125 MHz recovered clock is output as is or divided by 5
and output on RCLK2 depending on the setting of 16_2.12.
1 = Output recovered clock on RCLK2
0 = Do not output recovered clock on RCLK2
The highest numbered port with this bit set will output the
clock.
0x0
Retain
The 125 MHz recovered clock is output as is or divided by 5
and output on RCLK1 depending on the setting of 16_2.12.
1 = Output recovered clock on RCLK1
0 = Do not output recovered clock on RCLK1
Changes to this bit are disruptive to the normal operation;
therefore, any changes to these registers must be followed
0x0
Update by a software reset to take effect.
1 = Use SCLK as 25MHz source
0 = Use XTAL_IN/REF_CLKP/N as source
0x0
Update Reserved
0x0
Retain
Set to 0s
Changes to this bit are disruptive to the normal operation;
therefore, any changes to these registers must be followed
by a software reset to take effect.
This bit determines whether the MAC Interface powers down
0x1
Update when Register 0_0.11, 16_0.2 are used to power down the
device or when the PHY enters the cable detect state.
1 = Always power up
0 = Can power down
0x0
Retain
Set to 0s
4.1.29 MAC Specific Interrupt Enable Register - Page 2, Register 18
Bits
15:8
7
Field
Reserved
FIFO Over/
Underflow
Interrupt Enable
Mode
R/W
R/W
HW Rst SW Rst
0x00
Retain
000000000
Description
0x0
Retain
1 = Interrupt enable
0 = Interrupt disable
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