I347-AT4 Datasheet, PDF (121/148 Pages) Intel Corporation – Intel® Ethernet Network Connection I347-AT4 Datasheet

Electrical and Timing Specifications—I347-AT4
5.4.2
XTAL_IN/XTAL_OUT (CLK_SEL[1:0] = 10b or 11b¹) Timing²
Over a full range of values listed in Section 5.1 unless otherwise specified.
Symbol
Parameter
Condition
Min
Typ
Max
Units
T_{P_XTAL_IN}
XTAL_IN Period
40
-50 ppm
40
40
+50 ppm
ns
T_{H_XTAL_IN}
XTAL_IN High time
13
20
27
ns
T_{L_XTAL_IN}
XTAL_IN Low time
13
20
27
ns
T_{R_XTAL_IN}
XTAL_IN Rise
10% to 90%
-
3.0
-
ns
T_{F_XTAL_IN}
XTAL_IN Fall
90% to 10%
-
T_{J_XTAL_IN}
XTAL_IN total jitter¹
-
3.0
-
ns
-
200
ps²
1. PLL generated clocks are not recommended as input to XTAL_IN since they can have excessive jitter. Zero delay buffers are also
not recommended for the same reason.
2. In SGMII to Copper mode, Broadband peak-peak = 200 ps, 12 kHz to 20 MHz rms = 3 ps.
T_{P_XTAL_IN}
T_{H_XTAL_IN}
T_{L_XTAL_IN}
XTAL_IN
T_{R_XTAL_IN}
T_{F_XTAL_IN}
Figure 25. XTAL_IN/XTAL_OUT Timing
5.4.3
LED to CONFIG Timing
Symbol
T_{DLY_CONFIG}
Parameter
LED to CONFIG Delay
Condition
Min
0
Typ
Max
25
Units
ns
1. See Section 3.21 for details.
2. If the crystal option is used, ensure that the frequency is 25 MHz ± 50 ppm. Capacitors must be
chosen carefully. Refer to the application note supplied by crystal vendor.
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