I347-AT4 Datasheet, PDF (64/148 Pages) Intel Corporation – Intel® Ethernet Network Connection I347-AT4 Datasheet

I347-AT4—Device Functionality
DC Coupled
Fault
AC Testing
Sample 0
Positive
Leg
Negative
Leg
AC Testing
Sample 1
Positive
Leg
Negative
Leg
(DC) EXTEST
Sample 0
Positive
Leg
Negative
Leg
(DC) EXTEST
Sample 1
Positive
Leg
Negative
Leg
No Fault
0b
1b
1b
0b
0b
1b
1b
0b
1. A solid short to power is assumed. If the short has high inductance then a pulse can still be sent at the receiver and is mistaken
as a good connection.
2. A short on the positive and negative leg can have several behaviors on the test receiver. If both drivers cancel each other out
then output on both legs is zero. If one driver dominates the other then both legs are either both one or both zero. In any case,
the result is that both legs has the same value.
RX+
TX
RX
RX-
Figure 17. DC Coupled Connection
3.20
Interrupt
The INTn pin supports the interrupt function. INTn is active low.
Registers 18_0, 18_1, 18_2, 18_4, and 26_6.7 are the Interrupt Enable registers.
Registers 19_0, 19_1, 19_2, 19_4, and 26_6.6 are the Interrupt Status registers.
Registers 23_0 is the Interrupt Status summary registers. Register 23_0 lists the ports
that have active interrupts. Register 23_0 provides a quick way to isolate the interrupt
so that the MAC or switch does not have to poll register 19 for all ports. Reading
register 23_0 does not de-assert the INTn pin. Note that register 23_0 can be accessed
by reading register 23_0 using the PHY address of any of the four ports.
The various pages of register 18 and 26_6.7 are used to select the interrupt events
that can activate the interrupt pin. The interrupt pin will be activated if any of the
selected events on any page of register 18 or 26_67 occurs.
If a certain interrupt event is not enabled for the INTn pin, it will still be indicated by
the corresponding interrupt status bits if the interrupt event occurs. The unselected
events do not cause the INTn pin to be activated.
3.21
Configuring The I347-AT4
The I347-AT4 can be configured two ways:
• Hardware configuration strap options (unmanaged applications)
• MDC/MDIO register writes (managed applications)
All hardware configuration options can be overwritten by software except PHYADR[4:2]
and PHY_ORDER.
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