I347-AT4 Datasheet, PDF (61/148 Pages) Intel Corporation – Intel® Ethernet Network Connection I347-AT4 Datasheet

Device Functionality—I347-AT4
3.19.7
EXTEST_PULSE Instruction
The AC or DC JTAG test modes can be selected for each port individually by scanning in
the desired bit value into AC/DC select scan registers shown in the scan chain
(Table 24). When the AC/DC select is set to DC the EXTEST_PULSE instruction has the
same behavior as the EXTEST instruction.
When the AC/DC select is set to AC, the EXTEST_PULSE instruction has the same
behavior as the EXTEST instruction except for the behavior of the S_OUTP/N and
Q_OUTP/N pins.
As in the EXTEST instruction, the test stimulus must first be shifted into the boundary-
scan registers. Upon the execution of the EXTEST_PULSE instruction the S_OUTP and
Q_OUTP pins output the level specified by the test stimulus and S_OUTN and S_CLKN
pins output the opposite level.
However, if the TAP controller enters into the Run-Test/Idle state the S_OUTN and
Q_OUTN pins output the level specified by the test stimulus and S_OUTP and Q_OUTP
pins output the opposite level.
When the TAP controller exits the Run-Test/Idle state, the S_OUTP and Q_OUTP pins
again output the level specified by the test stimulus and S_OUTN and Q_OUTN pins
output the opposite level.
3.19.8
EXTEST_TRAIN Instruction
When the AC/DC select is set to DC, the EXTEST_TRAIN instruction has the same
behavior as the EXTEST instruction.
When the AC/DC select is set to AC, the EXTEST_TRAIN instruction has the same
behavior as the EXTEST instruction except for the behavior of the S_OUTP/N and
Q_OUTP/N pins.
As in the EXTEST instruction, the test stimulus must first be shifted into the boundary-
scan registers. Upon the execution of the EXTEST_PULSE instruction the S_OUTP and
Q_OUTP pins output the level specified by the test stimulus and S_OUTN and Q_OUTN
pins output the opposite level.
However, if the TAP controller enters into the Run-Test/Idle state the S_OUTP/N and
Q_OUTP/N will toggle between inverted and non-inverted levels on the falling edge of
TCK. This toggling will continue for as long as the TAP controller remains in the Run-
Test/Idle state.
When the TAP controller exits the Run-Test/Idle state, the S_OUTP and Q_OUTP pins
again output the level specified by the test stimulus and S_OUTN and Q_OUTN pins
output the opposite level.
3.19.9
AC-JTAG Fault Detection
The fault detection across AC coupled connections can be detected with a combination
of (DC) EXTEST and any one of the AC JTAG commands. The AC coupled connection is
shown in Figure 16. The fault signature is listed in Table 27. Column 1 lists the fault
type.
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