I347-AT4 Datasheet, PDF (35/148 Pages) Intel Corporation – Intel® Ethernet Network Connection I347-AT4 Datasheet

Device Functionality—I347-AT4
Table 10.
For the I347-AT4, the status of the FIFO can be interrogated as in Table 10. Registers
19_2.3:2 are set depending on whether the copper transmit FIFO inserted or deleted
idle symbols. Idles inserted or deleted will be flagged only if the inter packet gap is 24
bytes or less at the input of the FIFO. Inserted or deleted idles are ignored if the inter-
packet gap is greater than 24 bytes.
The FIFO status bits can generate interrupts by setting the corresponding bits in
register 18_1, 18_2, and 18_4.
I347-AT4 FIFO Status Bits
Register
19_2.7
19_2.3
19_2.2
Function
Copper Transmit FIFO Over/Underflow
Copper Transmit FIFO Idle Inserted
Copper Transmit FIFO Idle Deleted
Setting
1b = Over/Underflow error
0b = No FIFO error
1b = Idle inserted
0b = No idle inserted
1b = Idle deleted
0b = No idle deleted
FIFO 16_2.15:14
FIFO 16_1.15:14
Copper
SGMII
Figure 12. FIFO Locations
3.5
Resets
In addition to the hardware reset pin (RESETn) there are several software reset bits as
listed in Table 11.
Register 27_4.15 is a software bit that emulates the hardware reset. The entire chip is
reset as if the RESETn pin is asserted. Once triggered, registers are not accessible
through the MDIO until the chip reset completes.
The copper circuit is reset per port via register 0_0.15.
Register 20_6.15 resets the mode control, port power management, and generator and
checkers.
All the reset registers previously described are self cleared. However, register 20_6.9 is
not self clearing. When register 20_6.9 is set to 1b, registers in banks 8, 9, 10 and 11
are not accessible.
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