I347-AT4 Datasheet, PDF (19/148 Pages) Intel Corporation – Intel® Ethernet Network Connection I347-AT4 Datasheet

Pin Interface—I347-AT4
2.1.8
Master Clock/Reset
Pin #
Pin Name
J13
XTAL_IN
J14
XTAL_OUT
D13
D14
REF_CLKP
REF_CLKN
H13
H14
CLK_SEL[1]
CLK_SEL[0]
E3
RESETn
1. See Section 3.21 for details.
Pin
Type
I
O
I
I
I
Description
25 MHz Clock Input
25 MHz ± 50 ppm tolerance crystal reference or oscillator input.
XTAL_IN should be left floating when it is not used. When XTAL_IN is driven
directly from the oscillator or clock buffer, this pin should be ac-coupled with a
0.1 nF capacitor.
No additional AC capacitor is needed if a capacitor divider is already used for
level shifting.
25 MHz Crystal Output.
25 MHz ± 50 ppm tolerance crystal reference. XTAL_OUT should be left floating
when it is not used.
125 MHz/156.25 MHz Reference Clock Input Positive and Negative ± 50 ppm
tolerance differential clock inputs.
REF_CLKP/N are LVDS differential inputs with a 100 Ω differential internal
termination resistor.
If not used, REF_CLKP must be pulled high with a 1 KΩ resistor to 1.9V.
If not used, REF_CLKN must be pulled to GND with a 1 KΩ resistor.
Reference Clock Selection
00b = Reserved.
01b = Reserved.
10b = Use 25 MHz XTAL_IN/XTAL_OUT¹.
11b = Use 25 MHz XTAL_IN/XTAL_OUT.
CLK_SEL[1:0] must be connected to VDDOR for configuration high.
Hardware reset. XTAL_IN must be active for a minimum of 10 clock cycles before
the rising edge of RESETn. RESETn must be in inactive state for normal
operation.
1b = Normal operation
0b = Reset
2.1.9
Test
Pin #
Pin Name
L14
HSDACP
L13
HSDACN
K13
TSTPT
C8
TSTPTF
A5
TEST[1]
B5
TEST[0]
Pin
Type
O
O
O
Description
AC Test Point. Positive and Negative.
These pins are also used to bring out a differential TX_TCLK. Connect these pins
with a 50 Ω termination resistor to VSS for IEEE testing and debug purposes. If
debug and IEEE testing are not of importance, these pins can be left floating.
DC Test Point. The TSTPT pin should be left floating.
DC test point. The TSTPTF pin should be left floating.
I, PD
Test Control. This pin should be left floating.
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