I347-AT4 Datasheet, PDF (48/148 Pages) Intel Corporation – Intel® Ethernet Network Connection I347-AT4 Datasheet

I347-AT4—Device Functionality
3.13
3.14
Packet Generator
The I347-AT4 contains a very simple packet generator. Section 4.1.50 lists the I347-
AT4 Packet Generator register details.
The packet generator is enabled when:
Register 16_6.7:6 controls which path the packet generator is connected to.
If register 16_6.7:6 is set to 01b then the input into the SGMII is ignored and the
packet is generated onto the copper transmit path.
If register 16_6.7:6 is set to 10b then the copper receiver is ignored and the packet is
generated onto the SGMII output path.
If register 16_6.7:6 is set to 11b then the copper receiver or the SGMII is ignored.
Once enabled, a fixed length packet of 64- or 1518- byte frame (including CRC) is
transmitted separated by 12 bytes of IPG. The preamble length is 8 bytes. The payload
of the frame is either a fixed 5A, A5, 5A, A5 pattern or a pseudo random pattern. A
correct IEEE CRC is appended to the end of the frame. An error packet can also be
generated.
The registers are as follows:
• 16_6.7:6 — Packet generation enable. 00b = Normal operation, Else = Enable
internal packet generator
• 16_6.2 — Payload type. — 0b = Pseudo random, 1b = Fixed 5A, A5, 5A, A5,...
• 16_6.1 — Packet length. — 0b = 64 bytes, 1b = 1518 bytes.
• 16_6.0 — Error packet — 0b = Good CRC, 1b = Symbol error and corrupt CRC.
• 16_6.15:8 — Packet Burst Size. — 0x00 = Continuous, 0x01 to 0xFF = Burst 1 to
255 packets.
If register 16_6.15:8 is set to a non-zero value, then register 16_6.7:6 self clears once
the required number of packets are generated. Note that if register 16_6.7:6 is
manually set to 0b while packets are still bursting, the bursting ceases immediately
once the current active packet finishes transmitting. The value in register 16_6.15:8
should not be changed while 16_6.7:6 is set to a non-zero value.
RX_ER Byte Capture
Each time there is an RX_ER in the internal GMII interface the PHY captures four bytes
before RX_ER is asserted. Once the bytes preceding the RX_ER assertion are captured
into the registers, they are not over written by new errors and they are only cleared
after the registers are read.
There is one set of RX_ER capture registers. It captures the receive path of the copper
path. These capture registers are always running.
The copper path is accessed via register 20_2. The following description applies to the
copper path.
38