I347-AT4 Datasheet, PDF (83/148 Pages) Intel Corporation – Intel® Ethernet Network Connection I347-AT4 Datasheet

Programmer’s Visible State—I347-AT4
4.1.10 1000BASE-T Control Register - Page 0, Register 9
Bits
Field
Mode
HW
Rst
15:13 Test Mode
R/W
0x0
MASTER/SLAVE
12
Manual
Configuration
R/W
0x0
Enable
11
MASTER/SLAVE
Configuration
Value
R/W
See
Descr.
10
Port Type
R/W
See
Descr.
9
1000BASE-T
Full-Duplex
R/W
0x1
8
1000BASE-T
Half-Duplex
R/W
See
Descr.
SW Rst
Description
Retain
Update
Update
Update
Update
Update
TX_CLK comes from the RX_CLK pin for jitter testing in test
modes 2 and 3. After exiting the test mode, hardware reset
or software reset (Register 0_0.15) should be issued to
ensure normal operation. A restart of Auto-Negotiation will
clear these bits.
000 = Normal Mode
001 = Test Mode 1 - Transmit Waveform Test
010 = Test Mode 2 - Transmit Jitter Test (MASTER mode)
011 = Test Mode 3 - Transmit Jitter Test (SLAVE mode)
100 = Test Mode 4 - Transmit Distortion Test
101, 110, 111 = Reserved
A write to this register bit does not take effect until any of
the following also occurs:
Software reset is asserted (Register 0_0.15)
Restart Auto-Negotiation is asserted (Register 0_0.9)
Power down (Register 0_0.11, 16_0.2) transitions from
power down to normal operation
Copper link goes down.
1 = Manual MASTER/SLAVE configuration
0 = Automatic MASTER/SLAVE configuration
A write to this register bit does not take effect until any of
the following also occurs:
Software reset is asserted (Register 0_0.15)
Restart Auto-Negotiation is asserted (Register 0_0.9)
Power down (Register 0_0.11, 16_0.2) transitions from
power down to normal operation
Copper link goes down.
Upon hardware reset this bit takes on the value of SEL_MS.
1 = Manual configure as MASTER
0 = Manual configure as SLAVE
A write to this register bit does not take effect until any of
the following also occurs:
Software reset is asserted (Register 0_0.15)
Restart Auto-Negotiation is asserted (Register 0_0.9)
Power down (Register 0_0.11, 16_0.2) transitions from
power down to normal operation
Copper link goes down.
Register 9_0.10 is ignored if Register 9_0.12 is equal to 1.
Upon hardware reset this bit takes on the value of SEL_MS.
1 = Prefer multi-port device (MASTER)
0 = Prefer single port device (SLAVE)
A write to this register bit does not take effect until any of
the following also occurs:
Software reset is asserted (Register 0_0.15)
Restart Auto-Negotiation is asserted (Register 0_0.9)
Power down (Register 0_0.11, 16_0.2) transitions from
power down to normal operation
Link goes down
1 = Advertise
0 = Not advertised
A write to this register bit does not take effect until any of
the following also occurs:
Software reset is asserted (Register 0_0.15)
Restart Auto-Negotiation is asserted (Register 0_0.9)
Power down (Register 0_0.11, 16_0.2) transitions from
power down to normal operation
Copper link goes down.
Upon hardware reset this bit takes on the value of
C_ANEG[0].
1 = Advertise
0 = Not advertised
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