I347-AT4 Datasheet, PDF (72/148 Pages) Intel Corporation – Intel® Ethernet Network Connection I347-AT4 Datasheet

I347-AT4—Programmer’s Visible State
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Programmer’s Visible State
The IEEE defines only 32 registers address space for the PHY. In order to extend the
number of registers address space available a paging mechanism is used. For register
address 0 to 21, and 23 to 28 register 22 bits 7 to 0 are used to specify the page. For
registers 30 and 31 register 29 bits 5:0 are used to specify the page. There is no
paging for registers 22 and 29.
In this document, the short hand used to specify the registers take the form
register_page.bit:bit, register_page.bit, register.bit:bit, or register.bit.
For example:
Register 16 page 2 bits 5 to 2 is specified as 16_2.5:2.
Register 16 page 2 bits 5 is specified as 16_2.5.
Register 2 bit 3 to 0 is specified as 2.3:0.
Note that in this context the setting of the page register (register 22) has no effect.
Register 2 bit 3 is specified as 2.3.
Table 37 lists the register types used in the register map.
Table 37. Register Types
Type
Description
C
LH
LL
Retain
RES
RO
ROS
ROC
RW
RWC
RWR
Clear after read.
Register field with latching high function. If status is high, then the register is set to one and remains set
until a read operation is performed through the management interface or a reset occurs.
Register field with latching low function. If status is low, then the register is cleared to zero and remains
zero until a read operation is performed through the management interface or a reset occurs.
The register value is retained after software reset is executed.
Reserved for future use. All reserved bits are read as zero unless otherwise noted.
Read only.
Read only, Set high after read.
Read only clear. After read, register field is cleared.
Read and Write with initial value indicated.
Read/Write clear on read. All field bits are readable and writable. After reset or after the register field is
read, register field is cleared to zero.
Read/Write clear on read. All field bits are readable and writable. After reset, register field is cleared to 0.
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