I347-AT4 Datasheet, PDF (118/148 Pages) Intel Corporation – Intel® Ethernet Network Connection I347-AT4 Datasheet

I347-AT4—Electrical and Timing Specifications
Voffset (such as, common mode voltage) = internal bias - single-ended peak-peak
voltage swing. See Figure 21 for details.
If DC coupling is used with a CML receiver, then the DC levels are determined by a
combination of the MACs output structure and the device input structure shown in the
CML Inputs diagram in Figure 22. Assuming the same MAC CML voltage levels and
structure, the common mode output levels are determined by:
• Voffset (such as, common mode voltage) = internal bias - single-ended peak-peak
voltage swing/2. See Figure 22 for details.
• If DC coupling is used, the output voltage DC levels are determined by the AC
coupling considerations previously described, plus the I/O buffer structure of the
MAC.
CML Outputs
Internal bias¹
50 ohm
50 ohm
V = Internal bias - Vpeak
S_OUT+
S_OUT-
(opposite of
S_OUT+)
AC coupling Cap.
V = Voffset
I_sink
1. Internal bias is generated from the
AVDDH supply and is typically 1.4V.
Internal bias - Vpeak
S_OUTP
Vpeak
Single-ended Voltage details
V = Voffset (i.e., common mode voltage) = Internal bias - Vpeak-peak
Vmin = Internal bias - 3 * Vpeak
Vmin must be greater than 700 mV
S_OUTN
Figure 21. AC Connections (CML or LVDS Receiver) or DC Connection LVDS Receiver
108