I347-AT4 Datasheet, PDF (67/148 Pages) Intel Corporation – Intel® Ethernet Network Connection I347-AT4 Datasheet

Device Functionality—I347-AT4
MDC
MDIO
(STA)
0 1 1 0 A4 A3 A2 A1 A0 R4 R3 R2 R1 R0 ^Z
MDIO
(PHY)
0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
IDLE
START
OPCODE
(Read)
PHY Address
Register Address
TA
Register Data
IDLE
Figure 18. Typical MDC/MDIO Read Operation
MDC
MDIO
(STA)
0 1 0 1 A4 A3 A2 A1 A0 R4 R3 R2 R1 R0 1 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
IDLE
START
OPCODE
(Write)
PHY Address
Register Address
TA
Register Data
IDLE
Figure 19.
Typical MDC/MDIO Write Operation
Table 33 is an example of a read operation.
Table 33. Serial Management Interface Protocol
32-Bit
Preamble
Start of
Frame
OpCode
Read = 10b
Write = 01b
5-Bit
PHY
Device
Address
5-Bit
PHY
Register
Address
(MSB)
2-Bit
Turn
around
Read = z0b
Write = 10b
16-Bit
Data Field
Idle
11111111b 01b
10b
01100b
00000b
z0b
0001001100000000b 11111111b
3.21.3.1
Extended Register Access
The IEEE defines only 32 registers address space for the PHY. In order to extend the
number of registers address space available a paging mechanism is used. For register
address 0 to 21, and 23 to 28 register 22 bits 7 to 0 are used to specify the page. For
registers 30 and 31 register 29 bits 5:0 are used to specify the page. There is no
paging for registers 22 and 29.
In this document, the short hand used to specify the registers take the form
register_page.bit:bit, register_page.bit, register.bit:bit, or register.bit.
For example:
Register 16 page 2 bits 5 to 2 is specified as 16_2.5:2.
Register 16 page 2 bits 5 is specified as 16_2.5.
Currently there it takes four MDIO write commands to write the same register to the
same value on all four ports. Register 22.15:14 can be used to selectively ignore
PHYAD[4:2] and PHYAD[1:0] as listed in Table 34 so that the same register address can
be written to all four ports in one MDIO write command. PHYAD[4:0] is still decoded for
read commands.
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