I347-AT4 Datasheet, PDF (85/148 Pages) Intel Corporation – Intel® Ethernet Network Connection I347-AT4 Datasheet

Programmer’s Visible State—I347-AT4
4.1.13 Copper Specific Control Register 1 - Page 0, Register 16
Bits
Field
15
Disable Link
Pulses
Mode
HW
Rst
R/W
0x0
14:12
Downshift
counter
R/W
0x3
11
Downshift
Enable
R/W
0x0
10
Force Copper
Link Good
R/W
0x0
9:8
Cable Detect
R/W
See
Descr.
7
Enable Extended
Distance
R/W
0x0
6:5
MDI Crossover
Mode
R/W
See
Descr.
4
Reserved
Copper
3
Transmitter
Disable
R/W
0x0
R/W
0x0
2
Power Down
R/W
0x0
SW Rst
Description
0x0
Update
Update
Retain
Update
Retain
Update
Retain
1 = Disable Link Pulse
0 = Enable Link Pulse
Changes to these bits are disruptive to the normal operation;
therefore, any changes to these registers must be followed by
software reset to take effect.
1x, 2x, ...8x is the number of times the PHY attempts to
establish Gigabit link before the PHY downshifts to the next
highest speed.
000 = 1x 100 = 5x
001 = 2x 101 = 6x
010 = 3x 110 = 7x
011 = 4x 111 = 8x
Changes to these bits are disruptive to the normal operation;
therefore, any changes to these registers must be followed by
software reset to take effect.
1 = Enable downshift.
0 = Disable downshift.
If link is forced to be good, the link state machine is bypassed
and the link is always up. In 1000BASE-T mode this has no
effect.
1 = Force link good
0 = Normal operation
Upon hardware reset both bits takes on the inverted value of
DIS_SLEEP.
0x = Off
10 = Sense only on Receive (Cable Detect)
11 = Sense and periodically transmit NLP (Cable Detect)
When using cable exceeding 100m, the 10BASE-T receive
threshold must be lowered in order to detect incoming signals.
1 = Lower 10BASE-T receive threshold
0 = Normal 10BASE-T receive threshold
Changes to these bits are disruptive to the normal operation;
therefore, any changes to these registers must be followed by
a software reset to take effect.
Upon hardware reset bits defaults as follows:
ENA_XC Bits 6:5
0
01
1
11
00 = Manual MDI configuration
01 = Manual MDIX configuration
10 = Reserved
11 = Enable automatic crossover for all modes
Set to 0
Retain
1 = Transmitter Disable
0 = Transmitter Enable
Retain
Power down is controlled via register 0_0.11 and 16_0.2. Both
bits must be set to 0 before the PHY will transition from power
down to normal operation.
When the port is switched from power down to normal
operation, software reset and restart Auto-Negotiation are
performed even when bits Reset (0_0.15) and Restart Auto-
Negotiation (0_0.9) are not set by the user.
1 = Power down
0 = Normal operation
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