I347-AT4 Datasheet, PDF (66/148 Pages) Intel Corporation – Intel® Ethernet Network Connection I347-AT4 Datasheet

I347-AT4—Device Functionality
3.21.2
Table 31.
Pin
CONFIG[0]
CONFIG[1]
CONFIG[2]
CONFIG[3]
Table 32.
Configuration Mapping
Configuration Mapping
SER_LED
Bit3
Bit 2
Bit1
Bit 0
X
PHY_ORDER
PHYAD[4]
PHYAD[3]
PHYAD[2]
0b
SEL_MS
ENA_PAUSE
C_ANEG[1]
C_ANEG[0]
1b
Reserved
0b
S_ANEG
ENA_XC
DIS_SLEEP
PDOWN
1b
Reserved
X
Reserved, set to 0b
MODE[2]
MODE[1]
MODE[0]
I347-AT4 PDOWN Register Setting as a Function of MODE[2:0]
MODE[2:0]
xxx
000b
001b
010b
011b
100b
101b
110b
111b
PDOWN
0b
1b
1b
1b
1b
1b
1b
1b
1b
0_0.11
0b
1b
1b
0b
0b
0b
0b
1b
1b
0_1.11
0b
0b
0b
1b
1b
1b
0b
1b
1b
0_4.11
0b
0b
0b
0b
0b
0b
1b
0b
0b
3.21.3
Software Configuration - Management Interface
The management interface provides access to the internal registers via the MDC and
MDIO pins and is compliant with IEEE 802.3u clause 22. MDC is the management data
clock input and, it can run from DC to a maximum rate of 12 MHz. At high MDIO
fanouts the maximum rate can be decreased depending on the output loading. MDIO is
the management data input/output and is a bi-directional signal that runs
synchronously to MDC.
The MDIO pin requires a pull-up resistor in a range from 1.5 KΩ to 10 KΩ that pulls the
MDIO high during the idle and turnaround.
PHY address is configured during the hardware reset sequence. Refer to Section 3.21.1
for more information on how to configure PHY addresses.
Typical read and write operations on the management interface are shown in Figure 18
and Figure 19. All the required serial management registers are implemented as well as
several optional registers. A description of the registers can be found in Section 4.0.
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