I347-AT4 Datasheet, PDF (117/148 Pages) Intel Corporation – Intel® Ethernet Network Connection I347-AT4 Datasheet

Electrical and Timing Specifications—I347-AT4
5.3.3.2
Transmitter DC Characteristics
Table 40. Programming SGMII Output Amplitude
Register 26_2 Bits
Field
Description
Differential voltage peak measured.
Note that internal bias minus the differential peak voltage must be greater
than 700 mV.
000b = 14 mV
001b = 112 mV
2:0
SGMII Output
Amplitude
010b = 210 mV
011b = 308 mV
100b = 406 mV
101b = 504 mV
110b = 602 mV
111b = 700 mV
CML Outputs
Internal bias¹
CML Inputs
Internal bias¹
50 ohm
50 ohm
S_OUT+
S_OUT-
S_IN+
50 ohm
I_sink
1. Internal bias is generated from the
AVDDH supply and is typically 1.4V.
Internal bias
S_IN-
50 ohm
Figure 20. CML I/Os
5.3.3.3
Common Mode Voltage (Voffset) Calculations
There are four different main configurations for the SGMII interface connections. These
are:
• DC connection to an LVDS receiver
• AC connection to an LVDS receiver
• DC connection to an CML receiver
• AC connection to an CML receiver
If AC coupling or DC coupling to an LVDS receiver is used, the DC output levels are
determined by the following:
• Internal bias. See Section 3.2.5 and Figure 20 for details. (If AVDDH is used to
generate the internal bias, the internal bias value is typically 1.4V.)
• The output voltage swing is programmed by Register 26_2.2:0 (see Section 4.1).
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