I347-AT4 Datasheet, PDF (6/148 Pages) Intel Corporation – Intel® Ethernet Network Connection I347-AT4 Datasheet

I347-AT4 — Contents
Contents
1.0
Introduction ........................................................................................................................ 1
1.1 I347-AT4 Features ................................................................................................ 2
2.0
Pin Interface ....................................................................................................................... 4
2.1 Pin Assignment ..................................................................................................... 4
2.1.1 Signal Type Definitions ............................................................................ 4
2.1.2 Media Dependent Interface ...................................................................... 5
2.1.3 SGMI ........................................................................................................ 6
2.1.4 Reserved Pins .......................................................................................... 7
2.1.5 Management/Control................................................................................ 7
2.1.6 LED .......................................................................................................... 8
2.1.7 JTAG ........................................................................................................ 8
2.1.8 Master Clock/Reset .................................................................................. 9
2.1.9 Test .......................................................................................................... 9
2.1.10 References ............................................................................................. 10
2.1.11 Power and Ground ................................................................................. 10
2.1.12 Clocking ................................................................................................. 10
2.1.13 Pins I/O State at Various Test or Reset Modes...................................... 11
2.2 Pinouts (Top View) .............................................................................................. 11
2.2.1 Pin A1 Location ...................................................................................... 11
2.2.2 Pinouts (A1 Through P7)........................................................................ 12
2.2.3 Pinouts (A8 Through P14)...................................................................... 13
3.0
Device Functionality ......................................................................................................... 14
3.1 I347-AT4 Operation and Major Interfaces ........................................................... 16
3.2 Copper Media Interface....................................................................................... 16
3.2.1 Transmit Side Network Interface ............................................................ 17
3.2.2 Encoder .................................................................................................. 17
3.2.3 Receive Side Network Interface ............................................................. 18
3.2.4 Decoder.................................................................................................. 19
3.2.5 Electrical Interface.................................................................................. 20
3.2.6 SGMII Speed and Link ........................................................................... 21
3.2.7 SGMII TRR Blocking .............................................................................. 21
3.3 Loopback............................................................................................................. 21
3.3.1 System Interface Loopback.................................................................... 21
3.3.2 Line Loopback ........................................................................................ 22
3.3.3 External Loopback ................................................................................. 23
3.4 Synchronizing FIFO ............................................................................................ 24
3.5 Resets ................................................................................................................. 25
3.6 Power Management ............................................................................................ 26
3.6.1 Manual Power Down .............................................................................. 26
3.6.2 MAC Interface Power Down ................................................................... 26
3.6.3 Copper Detect Mode .............................................................................. 27
3.6.4 Low Power Modes.................................................................................. 28
3.6.5 Low Power Operating Modes ................................................................. 28
3.6.6 SGMII Effect on Low Power Modes ....................................................... 29
3.7 Auto-Negotiation ................................................................................................. 29
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