I347-AT4 Datasheet, PDF (54/148 Pages) Intel Corporation – Intel® Ethernet Network Connection I347-AT4 Datasheet

I347-AT4—Device Functionality
3.18.2
Serial LED
When the CLK_SEL[1:0] is set to 10b at the de-assertion of hardware reset and the
PTP_EN configuration bit is set to 1b, the serial LED mode is enabled. All regular LED
functions are disabled and registers 16_3, 17_3, 18_3, and 19_3 are ignored.
In the serial LED mode the data is clocked through a shift register and the shifted
values are output on the 16 LED pins when strobed.
CONFIG[1] is used as the data input.
CONFIG[2] is used as the clock.
CLK_SEL[0] is used as the strobe. Note that this pin must be set to 0b at the de-
assertion of hardware reset to enable the serial LED mode.
In addition to the above four pins register 27_4.9 is used to control whether all 16 LEDs
are tri-stated or not.
0b = Tristate
1b = Output (hardware default)
Register 27_4.11:10 determines how many LEDs per port are in the shift chain. In all
cases, P0_LED[0] is the last bit to be shifted in. (P3_LED[3] is the first bit to be shifted
in if 27_4.11:10 = 11).
00b = Shift through P0_LED[0], P1_LED[0], P2_LED[0], P3_LED[0].
01b = Shift through P0_LED[0], P0_LED[1], P1_LED[0], P1_LED[1], P2_LED[0],
P2_LED[1], P3_LED[0], P3_LED[1].
10b = Shift through P0_LED[0], P0_LED[1], P0_LED[2], P1_LED[0], P1_LED[1],
P1_LED[2], P2_LED[0], P2_LED[1], P2_LED[2], P3_LED[0], P3_LED[1], P3_LED[2].
11b = Shift through P0_LED[0], P0_LED[1], P0_LED[2], P0_LED[3], P1_LED[0],
P1_LED[1], P1_LED[2], P1_LED[3], P2_LED[0], P2_LED[1], P2_LED[2], P2_LED[3],
P3_LED[0], P3_LED[1], P3_LED[2], P3_LED[3]. (hardware default).
Register 27_4.13:12 determines at what point in the shift register chain should be
output to RCLK.
00b = Output after port 0.
01b = Output after port 1.
10b = Output after port 2.
1b1 = Output after port 3. (hardware default)
The initial value of the shift registers and the LED outputs are that LED[1] and LED[3]
output 0 and LED[0] and LED[2] output 1 for all ports.
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