I347-AT4 Datasheet, PDF (29/148 Pages) Intel Corporation – Intel® Ethernet Network Connection I347-AT4 Datasheet

Device Functionality—I347-AT4
3.2.3.6
Digital Adaptive Equalizer
The digital adaptive equalizer removes inter-symbol interference at the receiver. The
digital adaptive equalizer takes unequalized signals from ADC output and uses a
combination of Feed Forward Equalizer (FFE) and decision feedback equalizer (DFE) for
the best-optimized signal-to-noise (SNR) ratio.
3.2.3.7
Digital Phase Lock Loop
In 1000BASE-T mode, the slave transmitter must use the exact receive clock frequency
it sees on the receive signal. Any slight long-term frequency phase jitter (frequency
drift) on the receive signal must be tracked and duplicated by the slave transmitter;
otherwise, the receivers of both the slave and master physical layer devices have
difficulty canceling the echo and NEXT components. In the I347-AT4, an advanced DPLL
is used to recover and track the clock timing information from the receive signal. This
DPLL has very low long-term phase jitter of its own, thereby maximizing the achievable
SNR.
3.2.3.8
Link Monitor
The link monitor is responsible for determining if link is established with a link partner.
In 10BASE-T mode, link monitor function is performed by detecting the presence of
valid link pulses (NLPs) on the MDIP/N pins.
In 100BASE-TX and 1000BASE-T modes, link is established by scrambled idles.
If Force Link Good register 16_0.10 is set high, the link is forced to be good and the
link monitor is bypassed for 100BASE-TX and 10BASE-T modes. In the 1000BASE-T
mode, register 16_0.10 has no effect.
3.2.3.9
Signal Detection
In 1000BASE-T mode, signal detection is based on whether the local receiver has
acquired lock to the incoming data stream.
In 100BASE-TX mode, the signal detection function is based on the receive signal
energy detected on the MDIP/N pins that is continuously qualified by the squelch detect
circuit, and the local receiver acquiring lock.
3.2.4
Decoder
3.2.4.1
1000BASE-T
In 1000BASE-T mode, the receive idle stream is analyzed so that the scrambler seed,
the skew among the 4 pairs, the pair swap order, and the polarity of the pairs can be
accounted for. Once calibrated, the 4D PAM 5 symbols are converted to 9-bit symbols
that are then descrambled into 8-bit data values. If the descrambler loses lock for any
reason, the link is brought down and calibration is restarted after the completion of
auto-negotiation.
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