I347-AT4 Datasheet, PDF(109/148 Page) Intel Corporation – Intel® Ethernet Network Connection I347-AT4 Datasheet

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I347-AT4 Datasheet, PDF (109/148 Pages) Intel Corporation – Intel® Ethernet Network Connection I347-AT4 Datasheet

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Programmerâs Visible StateâI347-AT4

Bits

7:0

Field

Mode

Late Collision 65-

96 bytes

RO, SC

HW Rst SW Rst

Description

0x00

Retain

This counter increments by 1 when the PHY is in half-duplex

and a start of packet is received while the 65th to 96th bytes

of the packet are transmitted.

The measurement is done at the internal GMII interface. The

counter will not roll over and will clear on read.

4.1.55 Late Collision Counters 3 & 4 - Page 6, Register 24

Bits

Field

15:8

Late Collision

>192 bytes

7:0

Late Collision

129-192 bytes

Mode

RO, SC

HW Rst SW Rst

Description

0x00

Retain

This counter increments by 1 when the PHY is in half-duplex

and a start of packet is received after 192 bytes of the packet

are transmitted.

The measurement is done at the internal GMII interface. The

counter will not roll over and will clear on read.

This counter increments by 1 when the PHY is in half-duplex

and a start of packet is received while the 129th to 192nd

bytes of the packet are transmitted.

The measurement is done at the internal GMII interface. The

counter will not roll over and will clear on read.

4.1.56

Late Collision Window Adjust/Link Disconnect - Page 6,

Bits

Field

15:13

12:8

Reserved

Late Collision

Window Adjust

7:0

Link Disconnect

Mode

R/W

RO, SC

HW Rst SW Rst

Description

0x0

0x00

Retain

Set to 0s

Number of bytes to advance in late collision window.

0 = start at 64th byte, 1 = start at 63rd byte, etc.

This counter counts the number of times link status changed

from up to down.

The counter will not roll over and will clear on read.

4.1.57 Misc Test - Page 6, Register 26

Bits

Field

TX_TCLK Enable

14:13

12:8

Reserved

Temperature

Threshold

Temperature

Sensor Interrupt

Enable

Temperature

Sensor Interrupt

Mode

R/W

RO, LH

HW Rst SW Rst

Description

0x0

0x19

0x0

Retain

The highest numbered enabled port will drive the transmit

clock to the HSDACP/N pin.

1 = Enable

0 = Disable

Set to 0

Temperature in C = 5 x 26_6.4:0 - 25

i.e. for 100C the value is 11001

0x0

Retain

1 = Interrupt Enable

0 = Interrupt Disable

0x0

1 = Temperature Reached Threshold

0 = Temperature Below Threshold

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