I347-AT4 Datasheet, PDF (51/148 Pages) Intel Corporation – Intel® Ethernet Network Connection I347-AT4 Datasheet

Device Functionality—I347-AT4
3.18
If 1000BASE-T link is established register 21_5.3:0 reports the polarity on all four
pairs.
Polarity correction can be disabled by register write 16_0.1 = 1b. Polarity is then forced
to normal 10BASE-T mode.
FLP Exchange Complete with No Link
Sometimes when link does not come up, it is difficult to determine whether the failure
is due to the auto-negotiation Fast Link Pulse (FLP) not completing or from the 10/100/
1000BASE-T link not being able to come up.
Register 19_0.3 is a sticky bit that gets set to 1b each time the FLP exchange
completes but the link cannot be established for some reason. Once the bit is set, it is
cleared only by reading the register.
This bit is not set if the FLP exchange does not complete, or if link is established.
3.18.0.1 Compound LED Modes
Compound LED modes are defined in Table 18.
Table 18. Compound LED Status
Compound
Mode
Description
Activity
Copper Link
Link
Transmit activity or receive activity.
10BASE-T link OR 100BASE-TX link or 1000BASE-T link.
Copper link.
3.18.0.2
Table 19.
Speed Blink
When 16_3.3:0 is set to 0010b the LED[0] pin takes on the following behavior.
LED[0] outputs the sequence listed in Table 19 depending on the status of the link. The
sequence consists of eight segments. If a 1000 Mb/s link is established the LED[0]
outputs 3 pulses, 100 Mb/s 2 pulses, 10 Mb/s 1 pulse, and no link 0 pulses. The
sequence repeats over and over again indefinitely.
The odd numbered segment pulse duration is specified in 18_3.1:0. The even
numbered pulse duration is specified in 18_3.3:2 (Table 20).
Speed Blinking Sequence
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