I347-AT4 Datasheet, PDF (18/148 Pages) Intel Corporation – Intel® Ethernet Network Connection I347-AT4 Datasheet

I347-AT4—Pin Interface
2.1.6
LED
Pin #
F2
E1
E2
D1
H1
G1
G2
F1
K2
K1
J1
H2
M2
M1
L2
L1
L3
K3
P1
N1
Pin Name
P0_LED[3]
P0_LED[2]
P0_LED[1]
P0_LED[0]
P1_LED[3]
P1_LED[2]
P1_LED[1]
P1_LED[0]
P2_LED[3]
P2_LED[2]
P2_LED[1]
P2_LED[0]
P3_LED[3]
P3_LED[2]
P3_LED[1]
P3_LED[0]
CONFIG[3]
CONFIG[2]
CONFIG[1]
CONFIG[0]
J2
V18_L
E13
V18_R
C7
V12_EN
Pin
Type
Description
O
Parallel LED Output port 0.
O
Parallel LED Output port 1.
O
Parallel LED Output port 2.
O
Parallel LED Output port 3.
I
Global hardware configuration.
See Section 3.21 for details.
VDDOL voltage control.
I
Tie to VSS = VDDOL operating at 3.3V
Floating = VDDOL operating at 1.9V
VDDOR voltage control.
I
Tie to VSS = VDDOR operating at 3.3V
Floating = VDDOR operating at 1.9V
VDDOM voltage control.
I
Tie to VSS = VDDOM operating at 3.3V
Floating = VDDOM operating at 1.9V
2.1.7
JTAG
Pin #
G14
G13
G12
E12
D12
Pin Name
TDI
TMS
TCK
TRSTn
TDO
Pin
Type
I, PU
I, PU
I, PU
I, PU
O
Description
Boundary scan test data input. TDI contains an internal 150 KΩ pull-up resistor.
Boundary scan test mode select input. TMS contains an internal 150 KΩ pull-up
resistor.
Boundary scan test clock input. TCK contains an internal 150 KΩ pull-up resistor.
Boundary scan test reset input. Active low.
TRSTn contains an internal 150 KΩ pull-up resistor. For normal operation, TRSTn
should be pulled low with a 4.7 KΩ pull-down resistor.
Boundary scan test data output.
8