I347-AT4 Datasheet, PDF (41/148 Pages) Intel Corporation – Intel® Ethernet Network Connection I347-AT4 Datasheet

Device Functionality—I347-AT4
3.8
3.9
Once the I347-AT4 completes auto-negotiation, it updates the various status in
registers 1_0, 5_0, 6_0, and 10_0. Speed, duplex, page received, and auto-negotiation
completed status are also available in registers 17_0 and 19_0.
See Section 3 for more details.
Downshift Feature
Without the downshift feature enabled, connecting between two Gigabit link partners
requires a four-pair RJ-45 cable to establish 10, 100, or 1000 Mb/s link. However, there
are existing cables that have only two-pairs, which are used to connect 10 Mb/s and
100 Mb/s Ethernet PHYs. With the availability of only pairs 1, 2 and 3, 6, Gigabit link
partners can auto-negotiation to 1000 Mb/s, but fail to link. The Gigabit PHY repeatedly
goes through the auto-negotiation but fails 1000 Mb/s link and never tries to link at 10
Mb/s or 100 Mb/s.
With the downshift feature enabled, the I347-AT4 is able to auto-negotiation with
another Gigabit link partner using cable pairs 1, 2 and 3, 6 to downshift and link at 10
Mb/s or 100 Mb/s, whichever is the next highest advertised speed common between
the two Gigabit PHYs.
In the case of a three pair cable (additional pair 4, 5 or 7, 8 - but not both) the same
downshift function for two-pair cables applies.
By default, the downshift feature is turned off. Refer to register 16_0.14:11, which
describes how to enable this feature and how to control the downshift algorithm
parameters.
To enable the downshift feature, the following registers must be set:
• Register 16_0.11 = 1b — enables downshift
• Register 16_0.14:12 — sets the number of link attempts before downshifting
Fast 1000BASE-T Link Down Indication
Per the IEEE 802.3 Clause 40 standard, a 1000BASE-T PHY is required to wait 750 ms
or more to report that link is down after detecting a problem with the link. For metro
Ethernet applications, a fast failover in 50 ms is specified, which cannot be met if the
PHY follows the 750 ms wait time. This delay can be reduced by intentionally violating
the IEEE standard by setting register 26_0.9 to 1b.
The delay at which link down is reported can be selected by setting register 26_0.11:10
as follows:
• 00b = 0 ms
• 01b = 10 ± 2 ms
• 10b = 20 ± 2ms
• 11b = 40 ± 2ms
31