I347-AT4 Datasheet, PDF (56/148 Pages) Intel Corporation – Intel® Ethernet Network Connection I347-AT4 Datasheet

I347-AT4—Device Functionality
Table 23. TAP Controller OPCodes
Instruction
EXTEST
SAMPLE/PRELOAD
CLAMP
HIGH-Z
ID_CODE
EXTEST_PULSE
EXTEST_TRAIN
PROG_HYST
BYPASS
OpCode
0x00000000
0x00000001
0x00000010
0x00000011
0x00000100
0x00000101
0x00000110
0x00001000
0x11111111
The I347-AT4 reserves five pins called the Test Access Port (TAP) to provide test
access: Test Mode Select Input (TMS), Test Clock Input (TCK), Test Data Input (TDI),
and Test Data Output (TDO), and Test Reset Input (TRSTn). To ensure race-free
operation all input and output data is synchronous with the test clock (TCK). TAP input
signals (TMS and TDI) are clocked into the test logic on the rising edge of TCK, while
output signal (TDO) is clocked on the falling edge. For additional details refer to the
IEEE 1149.1 Boundary Scan Architecture document.
3.19.1
BYPASS Instruction
The BYPASS instruction uses the bypass register. This register contains a single shift-
register stage and is used to provide a minimum length serial path between the TDI
and TDO pins of the I347-AT4 when test operation is not required. This arrangement
allows rapid movement of test data to and from other testable devices in the system.
3.19.2
Table 24.
SAMPLE/PRELOAD Instruction
The SAMPLE/PRELOAD instruction enables scanning of the boundary-scan register
without causing interference to the normal operation of the I347-AT4. Two functions
are performed when this instruction is selected: sample and preload.
Sample enables a snapshot to be taken of the data flowing from the system pins to the
on-chip test logic or vice versa, without interfering with normal operation. The
snapshot is taken on the rising edge of TCK in the Capture-DR controller state, and the
data can be viewed by shifting through the component's TDO output.
While sampling and shifting data out through TDO for observation, preload enables an
initial data pattern to be shifted in through TDI and to be placed at the latched parallel
output of the boundary-scan register cells that are connected to system output pins.
This step ensures that known data is driven through the system output pins upon
entering the extest instruction. Without preload, indeterminate data would be driven
until the first scan sequence is complete. The shifting of data for the sample and
preload phases can occur simultaneously. While data capture is being shifted out, the
preload data can be shifted in.
Boundary Scan Chain Order
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