I347-AT4 Datasheet, PDF (60/148 Pages) Intel Corporation – Intel® Ethernet Network Connection I347-AT4 Datasheet

I347-AT4—Device Functionality
Pin
VDDC
AVDDH
DVDD
VSS
I/O
Power
Power
Power
Power
3.19.3
EXTEST Instruction
The EXTEST instruction enables circuitry external to the I347-AT4 (typically the board
interconnections) to be tested. Prior to executing the EXTEST instruction, the first test
stimulus to be applied is shifted into the boundary-scan registers using the sample/
preload instruction. Thus, when the change to the extest instruction takes place, known
data is driven immediately from the I347-AT4 to its external connections. Note that the
S_OUTP/N and Q_OUTP/N pins are driven to static levels. The positive and negative
legs of the S_OUTP/N and Q_OUTP/N pins are controlled via a single boundary scan
cell.The positive leg outputs the level specified by the boundary scan cell while the
negative leg outputs the opposite level.
3.19.4
The CLAMP Instruction
The CLAMP instruction enables the state of the signals driven from component pins to
be determined from the boundary-scan register while the bypass register is selected as
the serial path between TDI and TDO. The signals driven from the component pins do
not change while the clamp instruction is selected.
3.19.5
The HIGH-Z Instruction
The HIGH-Z instruction places all of the digital component system logic outputs in an
inactive high-impedance drive state. In this state, an in-circuit test system might drive
signals onto the connections normally driven by a component output without incurring
the risk of damage to the component.
3.19.6 ID CODE Instruction
The ID CODE contains the manufacturer identity, part and version.
Table 26. ID CODE Instruction
Version
Part Number
Manufacturer Identity
Bit 31 to 28
Bit 27 to 12
Bit 11 to 1
0
0000
0000000000001110
00111101110
1
50