I347-AT4 Datasheet, PDF (119/148 Pages) Intel Corporation – Intel® Ethernet Network Connection I347-AT4 Datasheet

Electrical and Timing Specifications—I347-AT4
CML Outputs
Internal bias¹
50 ohm
50 ohm
I_sink
1. Internal bias is generated from the
AVDDH supply and is typically 1.4V.
V = Internal bias
S_OUT+
S_OUT-
(opposite of
S_OUT+)
V = Voffset
V = Internal bias -
Vpeak-peak
CML Inputs
Internal bias¹
50 ohm
S_IN+
Internal bias
50 ohm
S_IN-
Internal bias
S_OUTP
Vpeak
Single-ended Voltage details
V = Voffset (i.e., common mode voltage) = Internal bias - Vpeak
Internal bias
Vmin = Internal bias - Vpeak-peak (single
ended)
(V min must be greater than 700 mV)
S_OUTN
Figure 22. DC Connection to a CML Receiver
5.3.3.4
Receiver DC Characteristics
Symbol
Parameter
Min
Typ
Max
Units
V_I
Input Voltage Range a or b
675
V_IDTH1
Input Differential Threshold
200
V_HYST1
Input Differential Hysteresis
25
R_IN
Receiver 100 Ω Differential Input
Impedance
80
1725
2100
120
mV
mV (peak-
peak
differential)
mV
Ω
1. Receiver is at high level when V_{S_INP} - V_{S_INN} is greater than V_IDTH(min) and is at low level when V_{S_INP} - V_{S_INN} is less than
-V_IDTH(min) . A minimum hysterisis of V_HYST is present between -V_IDTH and +V_IDTH as shown in Figure 23.
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