I347-AT4 Datasheet, PDF (126/148 Pages) Intel Corporation – Intel® Ethernet Network Connection I347-AT4 Datasheet

I347-AT4—Electrical and Timing Specifications
Over a full range of values listed in Section 5.1 unless otherwise specified.
Symbol
Parameter
Pins
Condition
Min
Typ
Max
Units
T_RISE
T_FALL
T_RISE/
TFALL
Symmetry
Rise time
Fall Time
MDIP/N[1:0]
MDIP/N[1:0]
MDIP/N[1:0]
DCD
Duty Cycle
Distortion
MDIP/N[1:0]
Transmit
Jitter
MDIP/N[1:0]
1. ANSI X3.263-1995 Figure 9-3.
100BASE-TX
100BASE-TX
100BASE-TX
100BASE-TX
100BASE-TX
3.0
4.0
5.0
ns
3.0
4.0
5.0
ns
0
0.5
ns
0
0.5¹
ns, peak-peak
0
1.4
ns, peak-peak
5.9
Latency Timing
5.9.1
10/100/1000BASE-T to SGMII Latency Timing
Over a full range of values listed in Section 5.1 unless otherwise specified.
Symbol
Parameter
Condition
Min
Typ
Max
Units
T_{AS_MDI_SERT}
X_1000
MDI SSD1 to S_OUTP/N
Start of Packet
292^1,2
336
ns
T_{DA_MDI_SERTX_}
1000
MDI CSReset, CSExtend,
CSExtend_Err to S_OUTP/
N/T/
292^1,2,3
336
ns
T_{AS_MDI_SERT}
X_100
MDI /J/ to S_OUTP/N Start
of Packet
620²
732
ns
T_{DA_MDI_SERTX_}
100
T_{AS_MDI_SERT}
X_10
MDI /T/ to S_OUTP/N/T/
MDI Preamble to S_OUTP/
N Start of Packet
620^2,3
4817^2,4
732
ns
5603
ns
T_{DA_MDI_SERTX_}
10
MDI ETD
to S_OUTP/N/T/
4817^2,3,4
5603
ns
1. In 1000BASE-T, the signals on the four MDI pairs arrive at different times because of the skew introduced by the cable. All timing
on MDIP/N[3:0] is referenced from the latest arriving signal.
2. Assumes Register 16.13:12 is set to 00b, which is the minimum latency. Each increase in setting adds 8 ns of latency
1000 Mb/s, 40 ns in 100 Mb/s, and 400 ns in 10 Mb/s.
3. Minimum and maximum values on end of packet assume zero frequency drift between the received signal on MDI and S_OUTP/
N. The worst case variation is outside these limits if there is a frequency difference.
4. Actual values depend on number of bits in preamble and number of dribble bits, since nibbles on MII are aligned to start of frame
delimiter and dribble bits are truncated.
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